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    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

IP Accelerated Initiative

Posted by Navraj Nandra on June 2nd, 2014

For this post, I’m stepping out of the world of analog/mixed-signal IP to look at some of the challenges faced by the SoC (system on chip) developers when they are using IP. Firstly, the software content is increasing – in some cases almost half of the development budget of an SoC is spent on software development. Secondly, more IP blocks, both PHY and link layer are required on the SoC. Today these are also pushing the speed envelope to 16 Gb/s for PCI Express Gen. 4 or DDR type memory interfaces running at 3200 Mb/s. Lastly, in order to ensure success of the IP on the SoC and also differentiate the IP, SoC developers are requesting integration services customized to their environment.

It is all about accelerating the time to market by reducing the development time, ensuring correctly working IP blocks from PHY, to link layer, to firmware.

In order to address these challenges, Synopsys today announced the “IP Accelerated Initiative”.  At a high level this initiative is comprised of the following (referring to the block diagram below):

  • IP prototyping kits that allow you to validate the IP in the exact configuration you want.

Reference implementation of the IP, that is based on HAP’s FPGA system with a PHY daughter card and this allows you to physical connect your USB for example through a cable to the device like a disk drive. This allows you to really exercise the system with the actually IP. But only part of the story, you can only validate hardware in the presence of software – like software drivers that make the hardware actually do something. In order to do this the prototyping kit comes with a 32 bit processor running linux which allows you to develop the drivers and middleware. There is a  fast iteration flow which is an automated methodology that allows you to go through the complete IP configuration space, create the exact configuration of the IP for your SoC and then you can download the bit-file representation directly onto the FPGA and this allows you validate the IP configuration in your system. The video shown here describes the implementation.

  • IP software development kits allows you to develop software that depends on that IP.

This uses a concept of virtual prototyping – this provides a virtual “target” to software developers, target is the term that software engineers use, so the software development can be done without the need of the actual hardware. To make this task efficient – or to accelerate it – the software development kit comes with reference drivers, a ported operating system. So the point is that the engineer can focus their task on software development rather than on putting the whole environment together. The video shown here provides an interesting demo of this flow.

  • Configuration and integration of IP to meet you specific implementation

We support customers through their unique SoC integration tasks that can include clock tree distribution, reset, power management, special side-band signals and test circuits. Since the SOC’s are getting very complex we can provide on-site support in terms of the customization, configuration and integration of the IP.

Addressing SoC Developers’ IP Challenges - It’s Not Just About the IP

The IP Accelerated initiative pulls together all the facets required to get the IP working and validated, allowing the SoC developers to focus on their  actual tasks of chip design.

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