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    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

Sharpen your FinFET memory test

Posted by Navraj Nandra on April 22nd, 2014

Last week at VLSI Test Symposium (VTS) 2014, Synopsys presented “Fault Modeling and Test Algorithm Creation Strategy for FinFET-Based Memories” to a packed room of attendees with several standing, all interested in learning about memory Test for FinFET.

FinFET transistors are playing an important role in advanced process technology nodes. Embedded memories based on FinFET transistors lead to new types of defects requiring new embedded test and repair solution. Due to the special structure of FinFET transistors, the existing fault models and detection techniques based on planar transistors are not enough to cover FinFET defects.

Synopsys has developed a new approach for investigation of FinFET-specific faults. In addition to fault modeling, a new methodology was also developed for test algorithm synthesis. The methodology has been validated on several real FinFET-based embedded memory technologies. Moreover, new faults have been identified that are specific only to FinFETs.

DesignWare® STAR Memory System, Synopsys' memory test, repair and diagnostics solution,

At Synopsys we’re very fortunate to work with Yervant Zorian and Samvel Shoukourian - the industry experts in semiconductor test. From 2000 to 2013, Yervant and Samvel worked on numerous publications and patents on testing of electronic devices and systems—particularly comprehensive embedded test, repair and diagnostic solutions for memories and other IP blocks in SoCs. The results of their work have been referenced by researchers more than 3,000 times and are widely used as a basis for further investigations in the area.

The integrated testing, recovering and diagnosing solutions for SoCs are used both during manufacturing and in system. These solutions are not only the basis for further research—but they have significant practical value.

They are used in two product lines developed by Synopsys and utilized in more than 300 companies. These products are DesignWare® STAR Memory System® (SMS) IP released in 2001 and DesignWare® STAR Hierarchical System® (SHS) IP released in 2013. Moreover, one of these products, SMS, was honored with the Best in Test Product of the Year award in 2002, and Test & Measurement World Best in Test Award in 2013.

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