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    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

Hierarchical system and IP test – vote for the true STAR!

Posted by Navraj Nandra on December 23rd, 2013

Synopsys’ DesignWare® STAR Hierarchical System has been selected by EDN as a Best in Test 2014 Award Finalist. Every year, the Best-in-Test Awards recognize the best in test products and test professionals. STAR Hierarchical System (SHS) has been nominated for “Best in Test Award” in two categories: “Best in Test 2014 – Semiconductor Test” and “Best in Test 2014 – Product of the Year”. Public voting decides the final winners, which will be announced at DesignCon 2014. This award is a great honor for a test product and you can help DesignWare STAR Hierarchical System win.

The DesignWare STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. The STAR Hierarchical System addresses increasing productivity and low-cost test requirements as SoC test becomes more complex as a result of larger designs and more extensive use of IP. The STAR Hierarchical System:

DesignWare STAR Hierarchical System improves test QoR and accelerate silicon testing of the entire SoC to meet cost, quality and schedule goals

  • Automatically creates a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, reducing test integration time and providing easy integration of the SoC test resources
  • Gives designers the flexibility to schedule individual IP/cores for parallel or serial testing to optimize test time and power consumption during test, which reduces test cost and increases test quality
  • Simplifies SoC test pattern creation and silicon debug using the IEEE 1500 network to port IP- or core-level patterns to the SoC level, and enabling the IP debug test modes from the SoC level
  • Helps improve SoC yield by enabling eFUSE programming for calibration and trimming of analog/mixed-signal IP
  • Offers design-for-test (DFT) implementation and hierarchical IP and core-level test that lets engineering teams cut their test integration time and bring their designs to market faster, with lower design and test cost

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