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    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

Multi-programmable non-volatile memory on standard 40-nm CMOS

Posted by Navraj Nandra on April 17th, 2013

A wide range of wireless SoCs supporting near field communication (NFC), Bluetooth, 802.11, and other radio applications can reduce both system power and cost by integrating multiple time programmable (MTP) non-volatile memory (NVM) on-chip. The MTP NVM can be used for field updatable lookup tables (for routing NFC packets), device matching (in the case of Bluetooth), customer settings (i.e., volume or radio pre-sets), or general configuration and calibration data.

While embedded MTP has been easily scalable from 350-nm to 65-nm, developing embedded MTP NVM in a standard CMOS process is becoming more difficult as the technology moves to more advanced nodes.

Embedded MTP is typically developed on the concept of storing charge on a floating gate. As the I/O voltage and corresponding gate oxide thickness reduces in advanced process nodes, the intrinsic ability of the process to store charge approaches the theoretical limit. Based on the work of Ielmini et. al1, in order to achieve 10-year data retention, the gate oxide needs to be above 44 angstrom, which falls between the typical gate oxide thickness for a 1.8V and a 2.5V transistor. Traditional embedded flash or embedded EEPROM technology normally requires additional processing which not only adds cost to the manufacturing process but may impact the device performance and may require design modifications to maintain the wireless or RF performance of the SoC. Synopsys’ DesignWare NVM IP addresses both the cost and design drawbacks by developing the IP in standard CMOS processes with no additional masks or processing steps. DesignWare IP has the added advantage of operating solely from the 1.1V supply, with all the necessary high voltage and support circuitry integrated in the NVM block itself.

Synopsys developed MTP in standard CMOS processes starting at 350-nm and now has silicon-proven embedded MTP in an industry leading 40-nm low power process. One of the key challenges in developing MTP in advanced process technologies is managing the stress put on the gate oxide during program and erase operations. At 40-nm, the most common I/O voltage has been reduced to 2.5V, and the gate oxide for these transistors is in the range of 50A. Reliably programming and erasing thousands of times requires a great deal of care and expertise. As I’ve mentioned before, Synopsys has the most thorough and comprehensive characterization and qualification methodology of any embedded NVM IP supplier. Already licensed to multiple customers targeting consumer and industrial wireless applications, Synopsys’ 40-nm embedded MTP is in the process of completing qualification testing and will be generally available within the next few months.

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