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    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

Free beer, a race track, FinFET’s, an IP summit, and memory test

Posted by Navraj Nandra on March 20th, 2013

Ok. So now I’ve got your attention :-) SNUG is where you will find all these and more!

Next Monday, Tuesday and Wednesday is our annual SNUG (Synopsys Users’ Group) at the Santa Clara Convention Center. Registration closes tomorrow noon-time (Thursday March 21st at 12PM – see registration link at the end of the post).

Monday will feature the IP Summit, comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries presented by Verisilicon and Imagination; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. Both days will provide ample opportunity to learn formally through tutorials, panels and presentations from customers and our R&D team on FinFET technology; and, informally through networking opportunities.

On Wednesday morning, my good friend and colleague, Dr. Yervant Zorian will deliver a tutorial on “Embedded Memory Test, Repair & Diagnostics”. He will address the very interesting topic facing SoC developers today, that yield relies heavily on memory yield. There is greater manufacturing complexity in 20-nm and FinFET technology nodes, which create new yield challenges, both in the form of increased defect densities and in the form of new types of failure mechanisms that need to be modeled for accurate detection, diagnosis, and repair. So, it is essential to have an embedded memory test and repair solution that not only meets the above challenges for today’s designs, especially those at 20-nm and below, but that is also cost-effective. Yervant will include a description of a new hierarchical embedded memory test and repair architecture, resulting in a 30% area reduction compared to the previous generation, support for high performance processor cores and advanced test, repair and diagnostics algorithms that target designs on advanced planar and FinFET technology nodes.

Oh, yes the beer and race track. Here are the details:

Where: SNUG Pub – The largest pub in silicon valley
When: Tuesday, March 26, 4:45 – 7:00 PM
What: SNUG Pub Grand Prix, you will be able to see our involvement in the automotive industry and will be able to test your driving skills and compete at the “SNUG Pub Grand Prix” at the Micro -Reality Race Track or the Daytona II Racing Simulators from 4:45 to 7:00 pm. It will be a great way to relax and have fun!

And…Yervant and I like beer and we love discussing what we do, so looking forward to seeing you next week.

SNUG registration closes tomorrow noon. Please visit www.synopsys.com and follow the links.

SNUG Pub - The largest pub is silicon valley - I know I've been to most of them!

SNUG Pub Racetrack

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