Posted by Navraj Nandra on March 18th, 2013
The MIPI M-PHY was developed for mobile devices where the important requirements were low pin count combined with very good power efficiency and high electro-migration interference (EMI) immunity. High performance is achieved through “gears”.
Gear 1 at 1.45 Gbps per lane, Gear 2 at 2.9 Gbps per lane and Gear 3 at 5.8 Gbps/lane. Mobile devices can be sensitive to EMI, and each gear of the M-PHY has two frequencies that are close together allowing to select the optimum from an radio receiver sensitivity perspective. Depending on your bandwidth needs you can go up to eight lanes. The picture below shows the M-PHY, it supports a number of protocols for different applications such as camera serial interfaces to camera sensors, internal displays, USB 3.0 or PCI Express protocols for chip to chip interfacing. For embedded storage, the next generation after the embedded multi-media card (eMMC) will be universal flash storage (UFS), a protocol the overlays the M-PHY.
So the point is that there are many applications and protocols that will use the MIPI M-PHY and the bandwidth needs are increasing. The latest specification to support the emerging bandwidth needs is Gear 3. This week during the MIPI Alliance face-to-face meeting in Asia, we will be demonstrating the first silicon proven M-PHY operating at High Speed Gear3.