Posted by Navraj Nandra on March 12th, 2013
We will be hosting our annual Synopsys user’s group meeting (SNUG) in Santa Clara this month. We will feature an IP Summit comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. You can register on
These tutorials provide insights into today’s IP development challenges and what may impact your design thinking in the future, propose solutions; presented by industry experts and this event will also provide a unique networking opportunity with IP developers, SOC design architects and system engineers.
I’m in the process of completing a tutorial “20-nm Mixed-Signal IP – A Stepping Stone to 16-nm FinFET?” (presented on Monday March 25th) I’m coming to the following conclusions, would be great to get your opinions too! Looking forward to seeing you.
1. Power, performance and area drives IP specifications for the analog/mixed-signal designer, these are achieved through architectural or schematic level design changes in advanced planar and FinFET designs
2. Analog process qualification vehicles are necessary to provide insight into the impact of the early design rules and process parameters on performance
3. FEOL impacts FinFET processes; key learning (stepping stone) from planar is DPT and device quantization
4. FinFET impacts analog parameters; completely new layout structures needed
5. Engineers will leverage FinFET physical properties and invent new circuits
You can register on http://www.synopsys.com/IP/Pages/ipsummit2013.aspx