Posted by Navraj Nandra on February 26th, 2013
Word has it that 14-nm or 16-nm fInFET processes are based on a planar CMOS 20-nm “back-end-of-line”. We’ll get into what back-end-of-line means in a later blog post. For now consider what the first statement implies since it is touted in the industry as a “fast and low risk ramp to finFET’s”, that the expertise developed for a 20-nm analog/mixed-signal IP design could be leveraged. But is this really be true? And is this the right question? IP reuse is about time to market, however, what an analog/mixed-signal designer really cares about is to get performance by the realization of higher fT and fmax, achieved by higher transconductance, output resistance, low gate capacitance and resistance. Nothing new here – this is our daily job as analog designers. The consumer of the IP, in many cases the SoC architect not only cares about time to market but also power, performance and area. Plus the IP must work on the first instantiation. The last two points are opening up new design possibilities for the analog designer. Going back thirty years, the initial CMOS circuits were based on the bipolar equivalents but over time new techniques such switched capacitor circuits started to appear as analog designers started to exploit the property of MOSFETS. We are at the same juncture with finFET’s.
The interconnects and dual pattern technology are similar to planar technologies but the devices are very different. In March, I will talking in more detail on this topic at SNUG San Jose. Going into how 20-nm planar designs require a much deeper link between layout and power, performance and area requirements compared to previous nodes. Furthermore, quantization of these devices means that the 20-nm planar development is from the ground up, so you can’t reuse even at the 28-nm node. I’ll be providing design examples and will let you determine whether 20-nm is truly a stepping stone to finFET’s.
Regardless, this is an exciting time to be analog/mixed-signal designer!