Posted by Navraj Nandra on February 12th, 2013
As many of my readers have experienced, getting your first silicon in the lab can be an exciting albeit nervous moment. In this post I am showing 20-nm silicon results – eye diagrams with excellent performance of some of the popular interface IP’s such as USB, PCI Express and MIPI. These all came up working first time on 20-nm in our characterisation labs. My engineering team did not leave anything to chance to ensure right first time results.
Let’s first look at the 20-nm process. The impact of this process on physical IP s had both challenges and benefits. The benefits included higher transition frequency (fT) and more transconductance (gm) of the transistor that enable faster designs with more gain. We also took the opportunity to re-design architectures to improve on power, performance and area at 20-nm. The challenges included new layout requirements that involve supporting double patterning technology (DPT), density requirements for metal and polysilicon, lower transistor output conductance (gd).
So how did we get it right? In order to ensure right first time silicon success, we developed an advanced silicon test-chip design methodology which solved two fundamental challenges of enabling 20-nm ready physical IP. The first is related to the CAD flow: the verification decks for design rule checking, metal filling, restricted density design rules below metal one, required significant changes to the infrastructure and management of the design database compared to 28-nm. The goal using this methodology is to prepare a 20-nm “pipe-cleaner” enabling faster design of the complex physical IP.
Due to aggressive time to market schedules, customers expected guarantees that physical IP blocks work on the first instantiation. This necessitated correlation between SPICE simulations and silicon characterization data of the fundamental IP building blocks such as transistors, capacitors and resistors of various aspect ratios. This is the second, and larger, challenge that is addressed in a test-chip before we develop the IP. This activity is only possible through deep collaboration with the foundry.
In the test-chip, a statistically meaningful number of devices was chosen to ensure the simulation to silicon correlation, this equated to 1500 devices with different layouts and density dependencies providing data for resistor / transistor matching and metal mismatch due to DPT. Ring oscillators and operational amplifiers gave early insight into the gate delay and analog performance of the 20-nm process. Metal-in-Metal (MiM) capacitor structures are also used. The methodology includes overstressing devices to evaluate the impact on reliability due to NBTI, PBTI and HCI. Electro-static discharge (ESD) structures are part of the physical IP and these needed to be designed for HBM and CDM performance – for example CDM must be tested across different voltage domains. In order achieve USB 2.0 compliance the 20-nm I/O need to support 5 V and these structures must also be implemented.
A current-to-voltage voltage converter for measuring the devices with better than 0.5% accuracy acts as the on-chip instrumentation and this is more than adequate for devices that typically have greater than 20% mis-match. A 4-pin JTAG interface allows full visibility and the 1500 devices can be tested in under two minutes.
So it came down to an advanced test chip methodology even before we started developing the interface IP and highly experienced analog/mixed-signal engineers to absorb, virtually in real-time, the PDK updates and to assess the impact on the designs.
The video describes this methodology too.