Posted by Navraj Nandra on October 4th, 2012
Some of our R&D colleagues and I will be presenting at TSMC’s OIP (Open Innovation Platform) Event in San Jose on 20-nm. We will describe new compact models that bridge design and manufacturing at 20-nm; implementation of dual patterning aware modeling and extraction; and, the engineering challenges of meeting power, performance and area targets of analog and physical IP such as USB, PCI Express and DDR. These presentations will be on October 16th starting at 1.30pm.
Joddy Wang will present “A Unified Compact Model Development Platform for 28nm & Beyond” The compact models of semiconductor devices are the bridge between design and manufacturing in the integrated circuit industry. Industry standard models released by the Compact Model Council (CMC) and its university development teams have successfully served the purpose well for the above-50nm nodes. For finer geometries, they are at most “base-line” models because of the lack of the models for such complex and yet critical effects as layout-dependent mechanical stress and proximity effects, parametric variability, DFM and restricted design rules, as well as device aging and reliability. Synopsys and TSMC came forward by jointly developing an industry/CMC standard application programming interface (API), TMI, to address these challenges. This paper will present the design and implementation, capability of TMI, as well as the interoperation of TMI with SPICE simulators. Finally, the advantages of using TMI for foundry PDK and reference flow development and deployment will be summarized.
Double patterning technology (DPT) has emerged as a critical technique for ensuring printability of device and interconnects layers in 20nm IC manufacturing. Bari Biswas presenting: “Double-Patterning Technology and Impact on 20nm Designs” will overview of the double patterning technology and discuss DPT aware modeling and extraction in Synopsys’ StarRC extraction solution, developed in close collaboration with TSMC. The presentation will cover both digital and custom design flows targeting TSMC’s 20nm process node and will also include a preview of the future 3D modeling capabilities for next-generation design.
I will present an “Advanced Silicon Design Methodology For Achieving 20nm Ready, Physical IP” The impact of the 20nm process on physical IP such as DDR4, PCI Express 3.0, USB 3.0 and data converters has its benefits and challenges to the design team. The benefits include higher transition frequency and more transconductance of the transistor that enable faster designs with more gain. Synopsys has developed an advanced silicon test-chip design methodology which solves two fundamental challenges of enabling 20nm ready physical IP. The first is related to the CAD flow: the verification decks for design rule checking, metal filling andrestricted density design rules below metal one, require signficant changes to the infrastructure and management of the design database compared to 28nm. The second and larger challenge, which is addressed in the test-chip, is the need to correlate between SPICE simulations and silicon characterization data of the fundamental IP blocks such as transistors, capacitors and resistors of various aspect ratios. This activity can only be achieved through extensive collaboration with TSMC, as a member of its OIP program.
Looking forward to meeting you in San Jose on the 16th!