I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! PCI Express Gen 3 Enters Prime Time – Opens New Markets
Posted by Navraj Nandra on 18th November 2010
Today, the final version of the PCI Express 3.0 (Generation 3) specification was released by the PCI Express Special Interest Group (PCI-SIG). With almost 1000 members and backed by companies such as Intel, HP, Oracle, AMD, Dell and Nvidia, this 8 Gb/s high speed serial interface will open new market opportunities in enterprise, data center and storage applications.
Three Generations Of PCI Express
Board member and chairman, Ramin Neshati, said that the new 8 Gb/s architecture will allow companies to build low-cost and power-efficient components and systems, could also be used for on-board components such as co-processors. The new specification could boost data transfers in high-performance systems, and data will get to storage devices and memory faster. He continued by saying that if a system builder is on a budget and has certain power consumption restrictions, they could build a server based on the second generation. For faster servers you could go with the third generation. Products designed around the latest specification will be able to achieve bandwidth near 1 GBps one direction on a single-lane configuration and scale to 32 GBps on a 16-lane configuration, Neshati said. He brought up an interesting point: that the new generation does not automatically replace the existing install base – it just targets a different market.
This begs the question on whether the previous generations will slowly disappear. From our market understanding, new opportunities are being created – especially driven by consumer connectivity in printers and wireless hubs. These applications only require the first PCI Express generation in a single lane, enabling the designer to trade off area, power and bandwidth. So, all three generations will survive – targetting specific markets. The above table provides a summary of the speed improvements.
In the enterprise market, at these high gen. 3.0 speeds, equalizers need to be used to counteract the effects of interference, cross-talk and high frequency noise. The type of equalization was a topic that was discussed extensively inside and outside the PCI-SIG. Power and area drove some of the decisions to include only a linear equalizer (CTLE) in the receiver for the PCI Express 3.0 PHY specifications. In evaluating the channel, that decision was re-thought, considering that there is a 10 mV eye-opening after the reference CTLE. In reality this means that the eye is closed. Under these conditions, decision feedback equalization DFE (either direct or unrolled) was a considered option. This will improve the PHY’s peformance but potentially impact power and area. In summary the CTLE boosts signal plus the noise, so SNR gets worse. DFE uses previous data bits to determine equalization and improves SNR.
Synopsys PCI Express Gen. 3 PHY Test-Chip
Further details on the complete solutions for all three generations of PCI Express can be found on http://www.synopsys.com/IP/InterfaceIP/PCIExpress/Pages/default.aspx
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