I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! Cost is the new IP design variable for DDR3 interfaces
Posted by Navraj Nandra on January 4th, 2010
For high speed memory interfaces, and for that matter any high speed interconnect such as source synchronous links or clock and data recovery SERDES – cost – coupled with power and speed have become the design targets. It is a bit like an optimization problem where the cost “variable” has a higher weighting. One of the main reasons is that these high performance interfaces initially designed for networking and high performance computer applications where cost had a lower weighting (over speed) now find their way into consumer devices.Â
Wire bond packages are often preferred for their lower cost yet flip chip packaging offers higher performance from a signal integrity perspective due to the lower inductance in the chip connectivity. One of the greatest challenges in any SoC that utilizes one or more high speed DDR3 channels (e.g., above 1066Mbps data rate) is the connection that the high-speed, parallel data channel DDR brings to the packaging technology and printed circuit board (PCB) design. Cost and power being the critical factors in consumer devices means that the IP vendor:
- Must not limit the IP in terms of using low cost packages and regular printed circuit boards
- Figure out the best power delivery characteristics
DDR3 is an example where speeds in the 1 Gb/s region will start to become common place in low cost consumer devices. So the design optimization challenge is to meet the speed using the most inexpensive package and the lowest number of PCB layers. In the following example this translates to using wirebond packaging and four layer PCB using through hole vias http://techon.nikkeibp.co.jp/article/HONSHI/20091126/178048/ where Synopsys’ DDR IP is implemented and validated at 1 Gb/s speeds.
With respect to power, poor power delivery characteristics can lead to effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion. This is described in more detail in http://synopsysoc.org/theeyeshaveit/?p=66
So the low cost consumer requirements in terms of the package type, PCB material and number of layers will dictate the future designs of DDR3 IP.
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As usual, this is a very relevant blog! When talking about DDR3, as you mention over 1Gbps frequency, the question which come to me, and I guess to the design community is: are we still talking about “soft” PHY (or I/O being part of a standard Library) or do we have to use a specially designed I/O, or custom PHY, available only from IP vendor?
Then, why? or why not?
Thanks!
For hyper competitive consumer applications cost has always been a hard boundary. The assumption is the technology can be made to fit, whether it be DDR3 or any other “high” performance IP. Usually there is some margin that can be exploited, because the consumer products usually follow and learn from the data applications. DDR3 is a case in point. I have recently worked on a very cost conscious consumer application with a DDR3-1600. Exactly the low cost PCB requirements Navraj describes…BUT Flip-chip packaging! It can be done…
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