Archive for 2010

Participating in the CEDIA (Custom Home Theater Installation Contractors) workshop is a classic example of how we approach each standard from grass roots level.

This was the first ever HDMI installer workshop with the goal of providing better insight into HDMI protocol and equipment connection sequences. We gained familiarity was various test instruments. We also learnt that most common problems in HDMI installations happen when an HDMI device (HDMI AVRs, HDMI switches, HDMI splitters, HDMI Cat6 Extenders etc) is inserted between 2 existing HDMI devices (set top box and digital TV). The device in the middle manipulates DTV’s EDID in various ways to reflect its limitations or improvements over DTV’s capabilities. Such daisy chaining does not work very well and troubleshooting the faulty component can be a night mare. We also saw some failures related to HDCP over poor quality cables. The bit errors during HDCP authentication corrupt the DDC channel and cause the authentication to fail.

Lessons learnt in such events are invaluable and our customers (and end consumers) reap the benefits of a robust interface that is a true “plug and play”.

Following on from last week’s posting on driving the HDMI ecosystem http://synopsysoc.org/theeyeshaveit/2010/10/hdmi-driving-an-ecosystem/ , this week I’m writing about an IP vendor’s perspective and the HDMI community:

1. HDMI is one of the key connectivity requirements in an SoC, the others include USB, DDR, PCI Express, SATA and MIPI
2. Complex multimedia SoCs require ~4 connectivity IPs. HDMI is a key component of multimedia ASICs along with other IPs like USB, DDR, and SATA etc.
3. Synopsys continues to see an increase in chip design starts requiring HDMI connectivity. This is consistent with the growing number of HDMI adopters (1000+) and HDMI enabled devices (1.5 Billion+). 
4. The range of applications is beyond traditional home theatre components like DTV, STB etc.
5. Mobile multimedia and home entertainment SOCs are primary markets for advanced nodes like 28 nm. HDMI is a key title required in these applications.
6. “Megatrends” like 3D will greatly enhance the demand for HDMI. Most multimedia SOCs designed in 2010 are incorporating this feature.
7. Other trends like home connectivity may continue to evolve HDMI in years to come.

Next week I will post the final installment on the HDMI ecosystem, by participating in workshops. A classic example of how we approach each standard (HDMI, USB, PCI Express) from the grass roots level is the Custom Home Theater Installation Contractors workshop.

Last week at the HDMI road show/developers conference in Sunnyvale, we showed the HDMI community how an IP provider can significantly impact and grow their eco-system.

 Back in 2002, there was a definitive need for digital connectivity for audio/video content. HDMI was there at the right place at the right time. As a result it has experienced a robust growth since its inception. With over 1.5 billion devices, it has definitely achieved “critical mass” and will continue to dominate over other competing standards. Since HDMI has achieved critical mass, by providing HDMI IP, Synopsys is playing a key role in ensuring that this protocol continues to flourish by enabling semiconductor companies aspiring to integrate HDMI connectivity into the latest generation of  40 nm and 32/28 nm SOCs. 

The end applications of these SOCs range from digital TVs, Blu Ray Players to very unique and un-tapped markets like 2D to 3D Boxes, 3D with glasses to 3D without glasses, 1080p to 4K resolution boxes, NAS systems etc. Boosted by the simplicity, reliability and performance of HDMI, these unique applications are sprawling all over the map to service this eco-system.

In my next posting I will show our opinions shared with the HDMI community from an IP vendors perspective.

Ralph Morgan, Our VP Engineering For HDMI Controllers

Flicking through an in-flight magazine this evening, my eye caught an ad with the title “Good-bye Sluggomorbus – Hello SuperSpeed USB” – it so happened I was on my way to a customer meeting to discuss – yes you got it – USB 3.0.

So the ad goes…”Sluggomorbus strikes when slow transfer rates make you wait for photos to upload…..symptoms include falling asleep, obscene gestures…”

Actually my meeting was to discuss the key considerations of integrating the USB 3.0 PHY into the customer’s chip, a topic that my readers would be interested in too.  So here goes… If you are thinking about USB 3.0 PHY integration the following decisions need to be made:

• Legacy support model
• Reference clock source selection
• Process/packaging technology selection
• Power-down requirements (what happens when the cable is NOT attached)
• Test & debug strategy

The key to understand the first bullet point is that USB 3.0 requires a new cable, basically 5 extra wires with differential receive and transmit pairs. The new SuperSpeed mode operates ten times faster than USB 2.0 – at an impressive 5Gb/s. This also requires simultaneous transmit and receive because USB 2.0 is bidirectional and this is where the legacy support comes into play. USB 3.0 must support 480 Mb/s high speed and full speed operation. Some customers think that using their existing USB 2.0 PHY & simply adding a SuperSpeed PHY, simplistically a 5 Gb/s SERDES, is a low risk solution to get to a complete backwardly compatible USB 3.0 implementation.

Not so.

With a completely integrated solution both the SuperSpeed and the USB 2.0 PHY’s come together as a single block. When done right this means that only a single input reference clock, a single external calibration resistor and a single USB 3.0 controller (link layer) is needed. This will handle all four speed modes of USB 3.0 from SuperSpeed to low speed. Also as I explained to the customer, Synopsys passed USB 3.0 compliance with our PHY’s and controllers and we offer a hardware validation platform of the entire solution using the Synplicity HAPS system.

So the only obscene gestures potentially come from a customer trying to figure out how to integrate the USB 3.0 5 Gb/s portion with the USB 2.0 PHY by themselves. 

Working on the analog front end for a consumer chip, one of the most important lessons I learnt from a senior engineer at Philips was that you got to figure out how to design analog on a standard digital CMOS process. Nowadays there’s a proliferation of consumer applications ranging from cell phones, computers, TVs and even digital picture frames are incorporating wireless communication transceivers to implement broadband standards such as LTE, WiMAX and WiFi to provide wireless connectivity to the outside world.

In order to save cost and have as many features squeezed in as possible, these SoC’s are manufactured in standard digital CMOS process using feature sizes from 65 nm to 28 nm.

These transceivers rely on an analog interface in the digital baseband processor System-on-Chip (SoC) to connect with the RF block. This analog interface is constantly evolving to adapt to the different communications standards.

Evaluating the specifications of these converters

you can see that performance is not changing significantly. The reason is that these converters are targetted for standard based systems: standards have long lifecycles. Therefore there is no need for faster or higher dynamic range. Power and area become the optimization targets.

The above shows the specification requirements for a communications ADC not changing over ten years but there have been improvements in power and area moving from 180 nm to 65 nm. 

More details on this topic as well as an understanding of the characteristics of the analog interfaces and why they are easy to integrate on the digital baseband SoC will be provided on the techonline webinar: http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_sep0910

This webinar will also give an overview of the constituent data converter IP blocks ADC for the receive (RX) path; DAC for transmit (TX) path; and phase locked loop (PLL) and how they can support multiple communication standards. Also providing tips on how these IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation.

So my boss comes into my office late last week and says: “we’re acquiring this company and you’re going to take care of the non-volatile memory business, ’cause its a bit like analog…” Synopsys Completes Acquisition of Virage Logic Corporation: http://synopsys.mediaroom.com/index.php?s=43&item=838

What an embedded non-volatile memory allows you to do is to store on an SoC, encryption keys, unique chip identification numbers, chip or system configuration data and even trim bits for on-chip analog components. The cool thing about this technology is that you can program it multiple times (to change encryption keys or the bios on your system, for example) and there are no special technology processing steps required. It can all be done in a standard CMOS process.

The number of programming cycles and data retention are couple of important considerations when evaluating embededd NVM. For robust automotive type applications a 10-year data retention at 150C is typically expected with about 1,000,000 write-erase cycles over the life of the memory. Yes that’s a million cycles at elevated temperature! Pretty impressive capability to have integrated into your SoC and this technology is already proven with the likes of Analog Devices, Sandisk and Richtek.

As Honda Su, Richtek’s technology executive puts it: “Other factors that attracted us included support for Bipolar/CMOS/DMOS (BCD) processes as it allows us to integrate non-volatile memory IP with high voltage devices in a single IC using a standard CMOS process with no additional masks or processing steps required. A nice additional capability was having all the required high voltage generated from within the IP block itself.”

The graph above summarizes typical applications into the NVM space

I’ll be posting more on this technology in the coming weeks and months but in the mean time here are some product briefs: http://www.synopsys.com/IP/EmbeddedMemories/Pages/AeonNoveaNvm.aspx

At yesterday’s Global Technology Conference in Santa Clara, California, GLOBALFOUNDRIES’ Gregg Bartlett presented a new high performance technology called 28 nm HPP. This is in addition to their gate first HKMG 28 LP, 28 SLP and 28 HP. 

The 28 HPP (HP plus) addresses the growing market for smart mobile devices and high-performance processors requiring more than 2 GHz of processing power. Scheduled to begin risk production in Q4 2011, this technology provides a performance boost of as much as 10% over the company’s current 28 nm High Performance (HP) offering, as well as offering optional ultra-low leakage transistors and SRAMs that extend the application range from high performance into the low power range.

This technology seems to compete with TSMC’s 28 HP(M) – high performance mobile – that was announced at the TSMC symposium in April.

With all these 28 nm process recipes or “HP sauces” on offer, engineers now have plenty of different choices to design high performance and low power devices.

Booting from a solid state drive (SSD) is much faster than the traditional hard disk drives and this is just one of the many reasons that the SSD’s have become popular in consumer devices. To assist developers of these products, one of our partners Global Unichip (GUC) has developed an SSD reference platform for mobile applications such as netbooks, mobile internet devices (MIDs) and high-speed pen drives. The connection to the netbook is made via the high performance SATA bus as shown below.

The GP5080 reference platform, provides developers with a low power, high data system throughput of more than 120 MB/s in sequential read and over 80 MB/s in sequential write with 4-channel NAND Flash access.

Translated into layman’s language this is bags faster than hard disk drives during booting.

Below is a block diagram of the reference platform

As well as the SATA interface, the GP5080 features a 32-bit ARM7 processor.  This provides firmware capability to improve the SSD’s performance in terms of lifetime and reliability by providing higher computing capability such as a flash translation layer, bad block management, wear leveling algorithm and power fail recycling.

As Dr. Thomas Hoffman from IMEC puts it, high-k metal gate “not only fixes the leakage problem but allows scaling to continue.” Transistors using the standard material used for the gate dielectric — silicon oxynitride (SiON) started seeing excessive leakage current at nodes below 90 nm. The alternative approach using high-k dielectrics can reduce gate leakage significantly, by orders of magnitude. 

There were compatibility issues with standard polysilicon gates that prevented transistors from switching properly at low threshold voltages, therefore high-k gate dielectrics are paired with a metal gate electrodes, hence the term high-k gate metal gate (HKMG). 

Two commercial manufacturing methods have emerged to integrate these materials namely “gate-first” and “gate-last” and are offered by GLOBALFOUNDRIES and TSMC respectively. Eager to capture 28 nm design starts both methods have been compared for both their merits and potential disadvantages. So which one does a design team choose for their 28 nm SoC?

HKMG Gate First, Gate Last

Dr Hoffmann articulates these differences in the above table. Essentially for low power applications gate-first is the better choice. However, for high performance applications the gate-last process with the faster transistors is more appropriate.