I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! Technology scaling a “virtuous cycle” for data converters
Posted by Navraj Nandra on November 5th, 2009
Had an interesting discussion with one of our data converter experts with respect to technology node scaling and it’s impact on an analog to digital converter. Manuel’s point is that a run-of-the-mill dual 10-bit, 80 MHz ADC in an 0.18 um technology is five times smaller in 65 nm. This is impressive. And like the USB PHY that I wrote about in my last posting, the size reduction has been achieved by architectural changes. This is what I learned from Manuel:
- Originally, ADC’s were designed using I/O (3.3 V) devices due to the higher voltage headroom that these devices enabled
- Presently all state-of-art ADCs are designed using core (1.2 V or lower) devices
- Although designing high performance converters at core voltage is challenging, it yields substantial gains in terms of maximum sampling rate, power dissipation and, obviously, area
Architectures have evolved significantly. Many design tricks are employed to reduce area. For example, by employing digital calibration schemes, it is possible to relax the performance of the individual analog blocks in the ADC. This makes those analog blocks (op-amps, comparators, etc) simpler and smaller – and less power consuming.
In the case of dual matched converters, Manuel said that it is possible to be very area effective by re-using a very high sampling rate single channel ADC to convert two channels at half speed. You’ll need to add a special front end stage that sample and holds the two channels in the same instant. An area saving of almost 50% can be achieved.
Note that, as for digital designs, there is a “virtuous cycle”  created by having a smaller design. If the converter is smaller, then the parasitic capacitances that it must drive are smaller and therefore the op-amp that drives them doesn’t need as much higher output drive and the commensurate biasing circuits that go with it are simpler, therefore even more area (and power) can be saved.
I’ll stop at this point. In my next posting, I will explore on how far we can go with this scaling. Where’s the limit? In the meantime you can read more about data coverters on  http://www.chipestimate.com/techtalk.php?d=2009-09-22
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Scaling down has advantages for circuits with large digital parts like sigma delta adc, pipelined ADC, where calibrating procedures could be used. Here is a point that some disadvantages of analog circuits could be recoverd by more complicated digital part.
With analog circuits one can expect lot of problems because some circuit topologies are simply not suitable. Instead of scaling I would say “The choose of right toplogy”.
However, for new circuits speed is usually one of the most important parameters, which means that new techologies has advantage.
In the opposite case when precision is the key factor I can not see much advantages.
Precision can be achieved in these technologies if you use the I/O (thick oxide) transistor.