Archive for November, 2009

In the last couple of postings I discussed technology scaling and it’s impact on analog IP.  The point is that like digital gates, analog IP benefits from technology scaling  but with a very different methodology – not using design tools but using different analog architectures: http://synopsysoc.org/theeyeshaveit/?p=242 illustrated USB 2.0 PHY scaling from 180 nm to 28 nm and http://synopsysoc.org/theeyeshaveit/?p=273 showed the example of a dual 10-bit, 80 MHz ADC in an 180 nm technology being five times smaller in 65 nm. So, if we go below 32/28 nm, will we continue to see this size reduction in analog IP?

Is there a size limit?

Our conjecture is that area improvements will happen, but not at the dramatic level as in the 180 nm to 65 nm example above. A couple of reasons for this:

• The advantages of moving from I/O devices to core devices has already been achieved with 65 nm technologies. Moving forward it will become harder and harder to design using sub-1V supplies and the designs will become more complicated in order to yield good performance at those low voltages. Most likely there will be only two transistors stacked with many more placed laterally. 
• The converters are now a very small fraction of the complete SoC area, even if, in some cases, multiple instantiations of the converter are used (for example, MIMO transceivers). Therefore there maybe no market driver/need

Of course, I’m saying this from today’s perspective. With new structures like finFET’s area and power may be further reduced.

CLEMENZA: “That Sonny’s runnin’ wild. He’s thinkin’a going to the mattresses already. We gotta find a spot over on the West Side”.

With LPDDR2 SDRAM beginning to garner design wins in mobile electronics, the next generation mobile DRAM is currently being debated. There are two camps: parallel and serial interfaces.

In order to support the higher speeds the technology proposed by the parallel camp is to use “TSV” or through silicon vias. Within the serial camp, there are two sub-groups: the “SPMT” and the “UFS MIPI M-PHY”. With the power and speed requirements the parallel interface, like most of the high speed interconnects, will go to a serial technology. Recognizing this, the debate is being focused on exactly which serial standard should be implemented.

While both have technical merits and some disadvantages the key difference is whether one of the standards is effectively a propriety technology – and potentially users of this version will have to pay a technology license or access fee. From a standards perspective this is just a bad idea (unless you are guy getting the license fee).

So the “serial war” is being played out and two camps will be on the mattresses for a while.

Had an interesting discussion with one of our data converter experts with respect to technology node scaling and it’s impact on an analog to digital converter. Manuel’s point is that a run-of-the-mill dual 10-bit, 80 MHz ADC in an 0.18 um technology is five times smaller in 65 nm. This is impressive. And like the USB PHY that I wrote about in my last posting, the size reduction has been achieved by architectural changes. This is what I learned from Manuel:

• Originally, ADC’s were designed using I/O (3.3 V) devices due to the higher voltage headroom that these devices enabled
• Presently all state-of-art ADCs are designed using core (1.2 V or lower) devices
• Although designing high performance converters at core voltage is challenging, it yields substantial gains in terms of maximum sampling rate, power dissipation and, obviously, area

Architectures have evolved significantly. Many design tricks are employed to reduce area. For example, by employing digital calibration schemes, it is possible to relax the performance of the individual analog blocks in  the ADC. This makes those analog blocks (op-amps, comparators, etc) simpler and smaller – and less power consuming.

In the case of dual matched converters, Manuel said that it is possible to be very area effective by re-using a very high sampling rate single channel ADC to convert two channels at half speed. You’ll need to add a special front end stage that sample and holds the two channels in the same instant. An area saving of almost 50% can be achieved.

Note that, as for digital designs, there is a “virtuous cycle”  created by having a smaller design. If the converter is smaller, then the parasitic capacitances that it must drive are smaller and therefore the op-amp that drives them doesn’t need as much higher output drive and the commensurate biasing circuits that go with it are simpler, therefore even more area (and power) can be saved.

I’ll stop at this point. In my next posting, I will explore on how far we can go with this scaling. Where’s the limit? In the meantime you can read more about data coverters on  http://www.chipestimate.com/techtalk.php?d=2009-09-22