I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! Implementing PCI Express in MicroTCA
Posted by Navraj Nandra on October 26th, 2009
MicroTCA and Advanced TCA are emerging standards for communications platforms in telecommunications and embedded applications. With over 100 companies contributing, the official specification for “Advanced Telecommunications Computing Architecture” specs the next generation of “carrier grade” communications equipment.
My involvement in this particular eco-system goes back about four years when I got excited about the attempt to standardize on specifications for the chassis, backplane architecture, fabrics, boards and mezzanine cards that reside in telco equipment. My thought was, if the equipment becomes standarized, then this will make the job of specifying the channel for interconnect protocols like PCI Express, SRIO (Serial Rapid IO) and gigabit Ethernet much easier. The advantage is that this enables manufacturers to work with an agnostic chassis backplane. The 10G backplane designs that currently use four lanes of 3.125 Gb/s will most likely drive the adoption of KR.
The MicroTCA Summit (October 27th to 29th, Santa Clara Convention Center) http://www.microtcasummit.com/, will bring together this eco-system to discuss the latest practical information and trends. I will be presenting the implementation of serial protocols like PCI Express and will begin with the fundamentals of the underlying technology that forms the SERDES physical, the transport and link layers.
Serial interconnects bring certain advantages to the MicroTCA systems, such as lower latency, QoS (quality of service) and on-board diagnostics. QoS is achieved via isochronous channels for guaranteed bandwidth delivery when required and lower latency through direct point-to-point connections. The on-board diagnostics enable the end user to evaluate the link performance in the chassis and make adjustments according to the channel characteristics.
Representing the next generation, PCI Express 2.0 and SRIO 2.0 effectively double the bandwidth to 5 Gb/s, these specifics will be also be further detailed in the presentation. So I hope to see you there!
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