Archive for October, 2009

Unlike digital transistors, scaling does not happen so readily or cleanly with analog blocks. The motivation to scale is driven by the fact that digital transistors scale quadratically with each process generation. There are many reasons that analog does not scale as readily. Mostly this is related to the fact the the I/O devices and passives, typically used extensively in analog circuits, do not scale from node to node.  So, is there any hope in benefiting from the process node scaling that we see in digital transistors?

The diagram above shows three generations Synopsys’ USB 2.0 PHY. As you can see we have managed to scale the design from the original 180 nm to today’s 28 nm version. Getting there wasn’t as simple as re-targeting standard cell libraries, followed by running automatic place and route. Scaling was achieved for this analog/mixed-signal IP and this was done by number of different design techniques.

The parameterized transistors cells were technology node optimized and much of the high speed analog circuitry was pushed to the low voltage core domain. The smaller technology nodes do have a higher poly sheet resistance per unit area and this helps in making the resistors smaller as well. The I/O voltage also scales from 3.3V to 1.8 V in 28 nm – this provides benefits in more efficient capacitor designs making the low pass filter in the PLLs, for example, much smaller. Of course you need to make due consideration to leakage, linearity and breakdown voltages.

So scaling can happen in analog too – but it is more than a push button operation.

More information on Synopsys’ latest USB 2.0 PHY on http://synopsys.mediaroom.com/index.php?s=43&item=745

MicroTCA and Advanced TCA are emerging standards for communications platforms in telecommunications and embedded applications. With over 100 companies contributing, the official specification for “Advanced Telecommunications Computing Architecture” specs the next generation of “carrier grade” communications equipment.

My involvement in this particular eco-system goes back about four years when I got excited about the attempt to standardize on specifications for the chassis, backplane architecture, fabrics, boards and mezzanine cards that reside in telco equipment. My thought was, if the equipment becomes standarized, then this will make the job of specifying the channel for interconnect protocols like PCI Express, SRIO (Serial Rapid IO) and gigabit Ethernet much easier. The advantage is that this enables manufacturers to work with an agnostic chassis backplane. The 10G backplane designs that currently use four lanes of 3.125 Gb/s will most likely drive the adoption of KR.

The MicroTCA Summit (October 27th to 29th, Santa Clara Convention Center) http://www.microtcasummit.com/, will bring together this eco-system to discuss the latest practical information and trends. I will be presenting the implementation of serial protocols like PCI Express and will begin with the fundamentals of the underlying technology that forms the SERDES physical, the transport and link layers.

Serial interconnects bring certain advantages to the MicroTCA systems, such as lower latency, QoS (quality of service) and on-board diagnostics. QoS is achieved via isochronous channels for guaranteed bandwidth delivery when required and lower latency through direct point-to-point connections. The on-board diagnostics enable the end user to evaluate the link performance in the chassis and make adjustments according to the channel characteristics.

Representing the next generation, PCI Express 2.0 and SRIO 2.0 effectively double the bandwidth to 5 Gb/s, these specifics will be also be further detailed in the presentation. So I hope to see you there!

This is an exciting time for analog/mixed signal IP from the perspective of the skill sets needed to support the latest roadmaps. Let’s look at the skill sets first. Scaling back R&D spending on central engineering teams, in some cases abandoning these central teams altogether, has transitioned companies from making analog/mixed IP to buying. As a result, the analog design expertise is shifting from these companies into the IP vendors. And for very good reasons. The interface speeds have increased into the 8 Gb/s region and the 40 nm, 32/28 nm semiconductor process technologies are forcing new analog/mixed-signal design techniques in both making the IP work in itself but also in the SoC where it resides.

Now lets examine the roadmaps. Will a wide-band sigma delta analog to digital converter be the right choice for LTE applications? Is 205 MSPS enough for 1080p video front-ends and will an audio CODEC with 96 dB dynamic range be sufficient in consumer hungry Asian market? Where are interfaces like USB, HDMI and DDR headed? Are customers more interested in getting the latest USB 3.0 or PCI Express 3.0 logos, the fastest DDR3, on their product to gain a competitve edge. Or, do they want to go after the green conscious Energy Star market. For the same interfaces the specifcation and design goal changes. Instead of 5 Gb/s USB 3.0, the target is low power, low pin count USB 2.0, single lane PCI Express Gen. 1, and instead of a superfast DDR3, the requirement is DDR3L which saves power by using 1.35 V amplitudes. And which process technology do we build these analog/mixed-signal interfaces – making the wrong choice can seriously impact the profitability of the IP business. The questions are related to poly-silicon orientation, metal stack configurations and meeting 5 V tolerance for USB and HDMI compliance with 35 Angstrom gate oxides. I’ll be sharing some of this insight at the SoC conference, Newport Beach, California. http://www.savantcompany.com/SoC7-Nov2009/main.htm

Assuming I get my part of the job right with the roadmap, what’s now needed are some very smart design engineers to build these IP’s. I’m very fortunate to be working with 450 of the industry’s best analog/mixed-signal design engineers on this roadmap.

Today we’re offering a number of very powerful silicon proven IP building blocks and customers now have at their finger tips the ability to build systems-on-chip. The system engineering task is becoming more complex, but we’re also offering more room for differentiation. And of course excitement!

In addition to scaling device sizes to 32/28 nm, the introduction of new process technologies is becoming a commercial reality. The two major semiconductor camps are vying for the high wafer volume of mobile interent devices and graphics. And their approaches to achieve low power, high speed without significant wafer costs are different. The discussion boils down to whether the CMOS process recipe that was used in 65 nm and 40 nm can meet these goals or, if a new technology is required. Extending the life of CMOS as we know it to 28 nm requires a strained channel for the conventional silicon oxynitride gate process (SION). The competing approach uses metal gate/high-k dielectrics (HKMG). In research labs thin body SOI and multi-gate transistor (FinFET) are also being considered.

HKMG is physically thick, to limit the gate leakage current, while being electrically thin, to provide adequate control over the transistor channel. The higher gate capacitance of the gate dielectric, allows a stronger electric field in the transistor channel and this resists the flow of electrons thereby reducing the subthreashold leakage. For longer metal interconnects airgap dielectrics reduce the capacitance – improving speed and lowering power consumption. The target is for high speed applications such as graphics.

SION on the other hand, has lower gate capacitance and this is good for designs with fewer metals and short interconnects, the target is for low power portable devices. Another advantage is that designers do not need to changer their circuits as SION is based of previous technology generations. 

This seems like a simple trade-off but the debate currently from the two semiconductor fabs is that low power can also be achieved with HKMG and adding a faster device to SION, the speed (of SION) can be improved…Ultimately, production with yield history will dictate whether one is better than the other.

The vision: use an optical fibre instead of a copper based cable for all connectivity on a laptop computer. The advantage: huge bandwidths that enable a consolidation of connectivity protocols over longer distances and potentially a connector/cable form factor that supports the thinnest of laptops. The demo: IDF (Intel’s Developers Forum) gave an idea of what is possible – 10 Gb/s bandwidth enabling uncompressed high definition video transfer over 40 m from a laptop to a monitor. http://www.eetimes.com/showArticle.jhtml?articleID=220200127

And that is the vision based on today’s technology. By increasing the wavelength of the light source to 2000 nm, even more bandwidth can be achieved, potentially allowing protocols such as PCI Express, HDMI, USB and SATA to be transferred through one fibre and one connector pair. OK if that’s not enough to carry the bandwidth just add another fiber. Imagine: the number of connectors going from say four or five to one.

Kudos goes to Intel for sharing this vision. The practicalities of making this work involve a complex multiplexing of disparate protocols, integrating optical transceivers into a low cost technology and bumping up the wavelength of the light source. Also developing the eco-system, from software drivers, transaction models, to board and connectors, can take many years. In the mean-time the focus is clearly on enabling protocols such as USB 3.0 to gain traction in the market. There is a humongous installed base of wired USB products in the market and it won’t be easy to replace them with optical connections.