In the run up to DAC (Design Automation Conference, San Francisco), I was asked to provide a 32 nm silicon proof point. It was a timely request as we’d just passed USB 2.0 silicon compliance with our 32 nm PHY. I spent last week showing the silicon results to the DAC attendees, got lots of questions on how we got the design to work (and pass silicon compliance). So here’s a summary of what I told the attendees. The main considerations for designing high performance analog/mixed-signal IP on a 32/28 nm process comes down to being able to model device degradation, designing for yield and being able to handle the effects of electromigration. In the case of USB 2.0 voltage stress is also an important consideration. The main device degradation effects are NBTI and HCI and these can be appropriately modeled in HSPICE. For yeild, the key is to be able to predict mis-match and offsets and incorporate them into your simulations. The influence of electromigration was through simulator we wrote using HSIM. Finally, the voltage stress on the 5V tolerant USB that used low voltage devices (5 V transistors are not available in 32/28 nm) was modeled using HSPICE. So the biggest secret at DAC has been revealed!

Compliant 32 nm USB 2.0 PHY