I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! Getting to the limits in wirebond packaging for DDR interfaces
Posted by Navraj Nandra on April 16th, 2009
In my last posting on this topic http://synopsysoc.org/theeyeshaveit/?p=57, I introduced the challenge of supporting high speed DDR interfaces in wirebond package technology. Today I’ll write a bit more on the specifics.
Flip chip packages have signal integrity advantages over wire bond packages since flip chip offers lower inductance paths for power and ground, reducing noise on the power rails. There is also less crosstalk in the chip to package substrate connection since tiny bumps replace long wires. Because of the shorter connection, signals also see a more consistent impedance profile in flip chip. However, wire bond packages still play a prominent role in high data rate DDR applications because of their obvious cost advantages. DDR2 at 800 and 1067Mbps has been successfully implemented in wire bond and some 1333Mbps designs are emerging as well but such designs need to take great care to avoid field returns.
In my next posting I will describe the effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion.
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