Archive for 2009

The reason for HDMI’s success was that it had all the right players in the eco-system. These included motion picture producers like FOX and DISNEY, the system operators Direct TV and Dish Network and consumer electronics giants such as Toshiba, Philips and Sony. But what was restricting further growth (or competition) was the limited number of semiconductor suppliers “in the know” to serve this eco-system. In what one author termed as a “self serving synergy”, the HDMI specification would be developed behind closed doors, giving an edge to those privy to the latest specifications. The rest of the semiconductor competitors would hence be playing a catch up game.  Before the competition could get ready, the new revision to the specification would be released, and the cycle continued…

HDMI has done an excellent job of future proofing itself. It has always been ahead of the game in terms of anticipating the next generation features of digital home theatre systems and other multi-media devices. The specification has evolved at a much faster pace compared to the other connectivity protocols like USB, DDR, SATA or PCI Express. New  features such as HEAC and 3-D mode incorporated into the 1.4 specification open new possibilities, for example ethernet connectivity.  However some education is needed as consumers and manufacturers will need to trade-off upgrading their systems for features that may (or not) necessarily be beneficial. To address this we were one of the first vendors to properly document the 1.4 use cases and implementation schemes and this has been appreciated by the eco-system.

With the rapid adoption and commoditization of HDMI, the number of startup companies serving this market has increased significantly. IP companies, like Synopsys are starting to play a very important role to serve this eco-system.  Using the HAPS 51 evaluation platform, our field application engineers are equipped to give HDMI hardware demonstrations using Synopsys PHY and controller IP, further enabling this eco-system.

For time to market reasons, and due to the fact that specification has evolved so rapidly, more and more SoC and system companies are deciding to purchase the HDMI IP. SoC and system designers are realizing that easy availability of HDMI IP in multiple process technologies is very essential to serve this high growth market. Ever since Synopsys acquired the MIPS Analog Business Group (ABG), we have leveraged the strengths of the two companies to penetrate into the HDMI eco-system. Inter-operability is a must for an IP provider, the CEC feature is an example which has caused difficultly for some vendors. Our recent achievements in ATC compliance - a 200 page tome with silicon characterization and plugfest report information highlights the commitment of Synopsys as an IP vendor to the eco-system. In fact, the consumer electronic giants are expecting certification reports as part of their qualification. As this market gets commoditized and fractured, there will be need for various process nodes to serve different applications. Companies like Synopsys will play a very key role in further enabling and expediting penetration of HDMI into multi-media devices.

What started as a discrete effort by a closed group, has truly gained global acceptance. However given the dynamics discussed above, a few players can no longer continue to dictate the market. As the number of HDMI ports has grown beyond 1 billion worldwide, this market will now be served by various competing companies from all sections of the eco-system.

In the last couple of postings I discussed technology scaling and it’s impact on analog IP.  The point is that like digital gates, analog IP benefits from technology scaling  but with a very different methodology – not using design tools but using different analog architectures: http://synopsysoc.org/theeyeshaveit/?p=242 illustrated USB 2.0 PHY scaling from 180 nm to 28 nm and http://synopsysoc.org/theeyeshaveit/?p=273 showed the example of a dual 10-bit, 80 MHz ADC in an 180 nm technology being five times smaller in 65 nm. So, if we go below 32/28 nm, will we continue to see this size reduction in analog IP?

Is there a size limit?

Our conjecture is that area improvements will happen, but not at the dramatic level as in the 180 nm to 65 nm example above. A couple of reasons for this:

• The advantages of moving from I/O devices to core devices has already been achieved with 65 nm technologies. Moving forward it will become harder and harder to design using sub-1V supplies and the designs will become more complicated in order to yield good performance at those low voltages. Most likely there will be only two transistors stacked with many more placed laterally. 
• The converters are now a very small fraction of the complete SoC area, even if, in some cases, multiple instantiations of the converter are used (for example, MIMO transceivers). Therefore there maybe no market driver/need

Of course, I’m saying this from today’s perspective. With new structures like finFET’s area and power may be further reduced.

CLEMENZA: “That Sonny’s runnin’ wild. He’s thinkin’a going to the mattresses already. We gotta find a spot over on the West Side”.

With LPDDR2 SDRAM beginning to garner design wins in mobile electronics, the next generation mobile DRAM is currently being debated. There are two camps: parallel and serial interfaces.

In order to support the higher speeds the technology proposed by the parallel camp is to use “TSV” or through silicon vias. Within the serial camp, there are two sub-groups: the “SPMT” and the “UFS MIPI M-PHY”. With the power and speed requirements the parallel interface, like most of the high speed interconnects, will go to a serial technology. Recognizing this, the debate is being focused on exactly which serial standard should be implemented.

While both have technical merits and some disadvantages the key difference is whether one of the standards is effectively a propriety technology – and potentially users of this version will have to pay a technology license or access fee. From a standards perspective this is just a bad idea (unless you are guy getting the license fee).

So the “serial war” is being played out and two camps will be on the mattresses for a while.

Had an interesting discussion with one of our data converter experts with respect to technology node scaling and it’s impact on an analog to digital converter. Manuel’s point is that a run-of-the-mill dual 10-bit, 80 MHz ADC in an 0.18 um technology is five times smaller in 65 nm. This is impressive. And like the USB PHY that I wrote about in my last posting, the size reduction has been achieved by architectural changes. This is what I learned from Manuel:

• Originally, ADC’s were designed using I/O (3.3 V) devices due to the higher voltage headroom that these devices enabled
• Presently all state-of-art ADCs are designed using core (1.2 V or lower) devices
• Although designing high performance converters at core voltage is challenging, it yields substantial gains in terms of maximum sampling rate, power dissipation and, obviously, area

Architectures have evolved significantly. Many design tricks are employed to reduce area. For example, by employing digital calibration schemes, it is possible to relax the performance of the individual analog blocks in  the ADC. This makes those analog blocks (op-amps, comparators, etc) simpler and smaller – and less power consuming.

In the case of dual matched converters, Manuel said that it is possible to be very area effective by re-using a very high sampling rate single channel ADC to convert two channels at half speed. You’ll need to add a special front end stage that sample and holds the two channels in the same instant. An area saving of almost 50% can be achieved.

Note that, as for digital designs, there is a “virtuous cycle”  created by having a smaller design. If the converter is smaller, then the parasitic capacitances that it must drive are smaller and therefore the op-amp that drives them doesn’t need as much higher output drive and the commensurate biasing circuits that go with it are simpler, therefore even more area (and power) can be saved.

I’ll stop at this point. In my next posting, I will explore on how far we can go with this scaling. Where’s the limit? In the meantime you can read more about data coverters on  http://www.chipestimate.com/techtalk.php?d=2009-09-22

Unlike digital transistors, scaling does not happen so readily or cleanly with analog blocks. The motivation to scale is driven by the fact that digital transistors scale quadratically with each process generation. There are many reasons that analog does not scale as readily. Mostly this is related to the fact the the I/O devices and passives, typically used extensively in analog circuits, do not scale from node to node.  So, is there any hope in benefiting from the process node scaling that we see in digital transistors?

The diagram above shows three generations Synopsys’ USB 2.0 PHY. As you can see we have managed to scale the design from the original 180 nm to today’s 28 nm version. Getting there wasn’t as simple as re-targeting standard cell libraries, followed by running automatic place and route. Scaling was achieved for this analog/mixed-signal IP and this was done by number of different design techniques.

The parameterized transistors cells were technology node optimized and much of the high speed analog circuitry was pushed to the low voltage core domain. The smaller technology nodes do have a higher poly sheet resistance per unit area and this helps in making the resistors smaller as well. The I/O voltage also scales from 3.3V to 1.8 V in 28 nm – this provides benefits in more efficient capacitor designs making the low pass filter in the PLLs, for example, much smaller. Of course you need to make due consideration to leakage, linearity and breakdown voltages.

So scaling can happen in analog too – but it is more than a push button operation.

More information on Synopsys’ latest USB 2.0 PHY on http://synopsys.mediaroom.com/index.php?s=43&item=745

MicroTCA and Advanced TCA are emerging standards for communications platforms in telecommunications and embedded applications. With over 100 companies contributing, the official specification for “Advanced Telecommunications Computing Architecture” specs the next generation of “carrier grade” communications equipment.

My involvement in this particular eco-system goes back about four years when I got excited about the attempt to standardize on specifications for the chassis, backplane architecture, fabrics, boards and mezzanine cards that reside in telco equipment. My thought was, if the equipment becomes standarized, then this will make the job of specifying the channel for interconnect protocols like PCI Express, SRIO (Serial Rapid IO) and gigabit Ethernet much easier. The advantage is that this enables manufacturers to work with an agnostic chassis backplane. The 10G backplane designs that currently use four lanes of 3.125 Gb/s will most likely drive the adoption of KR.

The MicroTCA Summit (October 27th to 29th, Santa Clara Convention Center) http://www.microtcasummit.com/, will bring together this eco-system to discuss the latest practical information and trends. I will be presenting the implementation of serial protocols like PCI Express and will begin with the fundamentals of the underlying technology that forms the SERDES physical, the transport and link layers.

Serial interconnects bring certain advantages to the MicroTCA systems, such as lower latency, QoS (quality of service) and on-board diagnostics. QoS is achieved via isochronous channels for guaranteed bandwidth delivery when required and lower latency through direct point-to-point connections. The on-board diagnostics enable the end user to evaluate the link performance in the chassis and make adjustments according to the channel characteristics.

Representing the next generation, PCI Express 2.0 and SRIO 2.0 effectively double the bandwidth to 5 Gb/s, these specifics will be also be further detailed in the presentation. So I hope to see you there!

This is an exciting time for analog/mixed signal IP from the perspective of the skill sets needed to support the latest roadmaps. Let’s look at the skill sets first. Scaling back R&D spending on central engineering teams, in some cases abandoning these central teams altogether, has transitioned companies from making analog/mixed IP to buying. As a result, the analog design expertise is shifting from these companies into the IP vendors. And for very good reasons. The interface speeds have increased into the 8 Gb/s region and the 40 nm, 32/28 nm semiconductor process technologies are forcing new analog/mixed-signal design techniques in both making the IP work in itself but also in the SoC where it resides.

Now lets examine the roadmaps. Will a wide-band sigma delta analog to digital converter be the right choice for LTE applications? Is 205 MSPS enough for 1080p video front-ends and will an audio CODEC with 96 dB dynamic range be sufficient in consumer hungry Asian market? Where are interfaces like USB, HDMI and DDR headed? Are customers more interested in getting the latest USB 3.0 or PCI Express 3.0 logos, the fastest DDR3, on their product to gain a competitve edge. Or, do they want to go after the green conscious Energy Star market. For the same interfaces the specifcation and design goal changes. Instead of 5 Gb/s USB 3.0, the target is low power, low pin count USB 2.0, single lane PCI Express Gen. 1, and instead of a superfast DDR3, the requirement is DDR3L which saves power by using 1.35 V amplitudes. And which process technology do we build these analog/mixed-signal interfaces – making the wrong choice can seriously impact the profitability of the IP business. The questions are related to poly-silicon orientation, metal stack configurations and meeting 5 V tolerance for USB and HDMI compliance with 35 Angstrom gate oxides. I’ll be sharing some of this insight at the SoC conference, Newport Beach, California. http://www.savantcompany.com/SoC7-Nov2009/main.htm

Assuming I get my part of the job right with the roadmap, what’s now needed are some very smart design engineers to build these IP’s. I’m very fortunate to be working with 450 of the industry’s best analog/mixed-signal design engineers on this roadmap.

Today we’re offering a number of very powerful silicon proven IP building blocks and customers now have at their finger tips the ability to build systems-on-chip. The system engineering task is becoming more complex, but we’re also offering more room for differentiation. And of course excitement!

In addition to scaling device sizes to 32/28 nm, the introduction of new process technologies is becoming a commercial reality. The two major semiconductor camps are vying for the high wafer volume of mobile interent devices and graphics. And their approaches to achieve low power, high speed without significant wafer costs are different. The discussion boils down to whether the CMOS process recipe that was used in 65 nm and 40 nm can meet these goals or, if a new technology is required. Extending the life of CMOS as we know it to 28 nm requires a strained channel for the conventional silicon oxynitride gate process (SION). The competing approach uses metal gate/high-k dielectrics (HKMG). In research labs thin body SOI and multi-gate transistor (FinFET) are also being considered.

HKMG is physically thick, to limit the gate leakage current, while being electrically thin, to provide adequate control over the transistor channel. The higher gate capacitance of the gate dielectric, allows a stronger electric field in the transistor channel and this resists the flow of electrons thereby reducing the subthreashold leakage. For longer metal interconnects airgap dielectrics reduce the capacitance – improving speed and lowering power consumption. The target is for high speed applications such as graphics.

SION on the other hand, has lower gate capacitance and this is good for designs with fewer metals and short interconnects, the target is for low power portable devices. Another advantage is that designers do not need to changer their circuits as SION is based of previous technology generations. 

This seems like a simple trade-off but the debate currently from the two semiconductor fabs is that low power can also be achieved with HKMG and adding a faster device to SION, the speed (of SION) can be improved…Ultimately, production with yield history will dictate whether one is better than the other.

The vision: use an optical fibre instead of a copper based cable for all connectivity on a laptop computer. The advantage: huge bandwidths that enable a consolidation of connectivity protocols over longer distances and potentially a connector/cable form factor that supports the thinnest of laptops. The demo: IDF (Intel’s Developers Forum) gave an idea of what is possible – 10 Gb/s bandwidth enabling uncompressed high definition video transfer over 40 m from a laptop to a monitor. http://www.eetimes.com/showArticle.jhtml?articleID=220200127

And that is the vision based on today’s technology. By increasing the wavelength of the light source to 2000 nm, even more bandwidth can be achieved, potentially allowing protocols such as PCI Express, HDMI, USB and SATA to be transferred through one fibre and one connector pair. OK if that’s not enough to carry the bandwidth just add another fiber. Imagine: the number of connectors going from say four or five to one.

Kudos goes to Intel for sharing this vision. The practicalities of making this work involve a complex multiplexing of disparate protocols, integrating optical transceivers into a low cost technology and bumping up the wavelength of the light source. Also developing the eco-system, from software drivers, transaction models, to board and connectors, can take many years. In the mean-time the focus is clearly on enabling protocols such as USB 3.0 to gain traction in the market. There is a humongous installed base of wired USB products in the market and it won’t be easy to replace them with optical connections.

Summer was a very busy time for me both professionally and personally. Looking back now both events were somewhat linked. Work-wise I was busy integrating Chipidea’s analog portfolio into Synopsys’ standards based PHY IP roadmap; personally I was challenged with learning the Waltz for the opening dance of my wedding.

Since May, we’ve been working on the integration of the former Chipidea analog portfolio into our very successful mixed-signal IP business. This meant figuring out an analog IP product roadmap for data converters (ADC’s, DAC’s), audio CODEC’s, video front-ends and touch-screen controllers. In a way, this was a “marriage” between our standards based interconnect roadmap (USB, PCI Express) with analog IP such as data converters that do not necessarily follow a particular standard specification. The goal of an IP company is to leverage as much engineering effort into standard based IP blocks. The good news is that over the past few months we have created a product roadmap for analog IP that not only follows the same principle as our interconnect roadmap but also matches our customer requirements in terms of the next generation of technnology nodes, data converter architectures and high performance audio/video IP.

Since there was an extensive analog IP portfolio existing at 65 nm, the decision was made to enhance the pipeline ADC’s and add wide-band sigma delta architectures to the 40 nm technology roadmap. With audio the goal is to continue enhancing the 96 dB, 103 dB platforms with lower power/area and adding Class D output stages. The video platform will support 3 channel 1080p WUXGA. There’s a couple of excellent introductory papers in our latest DesignWare Technical Bulletin that contain more information:

“Advanced audio drivers” https://www.synopsys.com/dw/dwtb.php?a=advanced_audio_drivers&elq=8e4455bc49944db393a466a7ffc9ec15

and

“Choosing the right architecture for analog-digital conversionin wireless communication broadband IC’s” https://www.synopsys.com/dw/dwtb.php?a=adc_in_wireless&elq=8e4455bc49944db393a466a7ffc9ec15

Oh, so now you’re asking…how were the two events linked? Well, having mastered the standard based waltz with its 1-2-3, 1-2-3 step to Strauss’ Blue Danube, we decided to mix in Punjabi MC rap into our wedding dance. Understanding the bangra rythmns and choreographing them into our waltz we created a new standard, much to the delight of our international audience!