I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! USB 2.0 PHY on 40 nm – What’s the big deal?
Posted by Navraj Nandra on 17th December 2008
So what’s the deal? If you look at USB 2.0 connector it has 4 pins: Dplus, Dminus, GND and 5V. For an embedded USB 2.0 PHY, the 5 V must be supported on the semiconductor technology that the rest of the chip uses. Today this is 65 or even 40 nm with 2.5 V or 1.8 V oxide. So the challenge is to build a circuit that can support 5V using a transistor, in the case of 40 nm, that has been only been rated to 1.8 V.
This requirement together with all the other electrical specifications is documented by the USB Implementers Forum. A couple of months ago we took our first USB 2.0 PHY test-chip design on TSMC’s 40 nm process using 1.8 V native devices to the USB sanctioned testing lab. We ran the 5 V short tolerance test for the required 24 hours. We passed this test and met all the other electrical requirements – meaning that the USB 2.0 PHY is certified to meet all the electrical requirements including 5 V tolerance. http://synopsys.mediaroom.com/index.php?s=43&item=636
So the question is…how did we do it? Well, come to my tutorial at the next SNUG and all will be revealed. (Well not quite all…just enough!)
Posted in General - mixed-signal IP | No Comments »
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