Archive for October, 2008

Getting analog functions on a chip that is mostly digital poses many challenges for the analog designer. Are they equipped? Look at it from the perspective of high speed interfaces that are needed on today’s digital 65- and 40 nm chips, like SERDES or DDR. The “prima donna” analog designers have had the luxury of supply voltages and process technology in their favour. But the bottom-line is can they design with these technologies and still meet performance in terms of tight jitter spec and sufficient link margins?

“As I was walking up the stair I met a man who wasn’t there. He wasn’t there again today.”

Was this man virtual? 

In the computer world, virtualization is a technique for hiding the physical computing resources from the way in which other systems, applications, or end users interact with those resources. This includes making a server or an operating system appear to function as multiple logical resources; or it can include making multiple physical resources (such as storage devices or servers) appear as a single logical resource.

The PCI Express protocol with I/O virtualization allows multiple operating systems running simultaneously within a single computer to share PCI Express devices. From the PCI-SIG website (http://www.pcisig.com/specifications/iov/)  These are grouped into three areas: 

• Address Translation Services (ATS): this specification provides a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O Virtualization.
• Single Root IOV: this specification provides native I/O Virtualization in existing PCI Express topologies where there is a single root complex.
• Multi-Root IOV: this specification builds on the Single Root IOV Specification to provide native I/O Virtualization in new topologies (such as blade servers) where multiple root complexes share a PCI Express hierarchy.

This functionality in the PCI Express protocol will enable network administrators virtualize or share peripherals and endpoints across different CPUs.

Any guesses on the author of the quote?

Well, it was a long summer break, since my last entry! Over the past few months, I spent quite a bit of time with customers around the globe learning about their fabrication technology needs. Here are the trends I’m seeing…

32 nm
- Reduction of product cost and power compared to 45 nm
- Foundry offerings include HKMG
- Migration started, leading IDM’s ramping up initial volumes in Q4/2009
- Ramp-up of 32 nm requires cost per function to be reduced (exception can be processors for high-end servers where price premiums can be maintained)
- Shrink path to 28 nm
- Mainstream market adoption projected in ~2012

45/40 nm
- 1st wave customers designing in 45/40nm
- Major driver: wireless handset/consumer multimedia
- Volumes low due to leakage (parametric yields, soft errors in embedded memory)
Mainstream market adoption in 2010~2011

65 nm
Very fast ramp-up of designs, faster than expected
Use of 65nm for RF as well as digital designs
Very long life cycle projected with Asia moving to 65 nm aggressively and 55 nm being offered in the digital consumer area

SOI
Still remains niche: GPU, CPU, NPU

Would be interesting to read your viewpoints.