Archive for 2008

So what’s the deal?  If you look at USB 2.0 connector it has 4 pins: Dplus, Dminus, GND and 5V. For an embedded USB 2.0 PHY, the 5 V must be supported on the semiconductor technology that the rest of the chip uses. Today this is 65 or even 40 nm with 2.5 V or 1.8 V oxide. So the challenge is to build a circuit that can support 5V using a transistor, in the case of 40 nm, that has been only been rated to 1.8 V.

This requirement together with all the other electrical specifications is documented by the USB Implementers Forum. A couple of months ago we took our first USB 2.0 PHY test-chip design on TSMC’s 40 nm process using 1.8 V native devices to the USB sanctioned testing lab. We ran the 5 V short tolerance test for the required 24 hours. We passed this test and met all the other electrical requirements – meaning that the USB 2.0 PHY is certified to meet all the electrical requirements including 5 V tolerance. http://synopsys.mediaroom.com/index.php?s=43&item=636

So the question is…how did we do it? Well, come to my tutorial at the next SNUG and all will be revealed. (Well not quite all…just enough!)

Analog/mixed-signal design on 45 nm was treated with some trepidation by one of the panelists at ICCAD last week: http://www.scdsource.com/article.php?id=319. See the section “45 nm? Don’t go there”. Contrary to the viewpoint of this panelist (who happens to be a friend and ex-colleague), it is possible to build robust high performance analog/mixed-signal on these leading edge digital CMOS technologies. And I have production silicon to prove my point! 

Let’s look at the differences between analog and digital design at 45 nm (and below). For digital design – the basic functionality scales. The NAND gate still looks the same. There is a significant density increase to allow you to do more – deal with more — but the devices, while tiny and fast, leak a lot, can’t be tunred off. And there is a lot of variation in timing. But in the end – most of the effort is focued on managing the power dissipated by all of the devices that aren’t doing anything. Plus the normal signal integrity and DFM concerns.

In analog design, the devices leak as well of course, they don’t perform as well as current sources, and there are physical reasons why it is difficult to make two devices identical. But some of the performance degradation due to the thinner gate oxide and smaller dimension can be mitigated by using the I/O device – the OLD analog transistor, if you will.

In this case you have to decide how to mix – higher voltage; lower voltage domains – trading off between the higher performance (speed) of thin gate deivces with the better precision of thick gate devices.

What becomes critical in the performance of analog design, is the sources of variation in the devices due to effects like shallow-trench isolation, well proximity, contact stress, phase shift mask correction algorithms, and then time dependent variation due to negative bias temperature instability in PMOS devices and hot carrier injection in NMOS devices. Once the impact of these are understood, you are well on your way of designing robust circuits in these advanced technology nodes.

Clearly, since the digital functionality scales so well – there is a huge advantage to moving everyting practical into the digital domain. For example, using a digitally controlled analog PLL. That means that the conventional PLL loop filter is implemented as a digital filter, a filter that now becomes insensitive to processing, voltage, and temperature.

It is also becoming necessary to have visibility into the analog domain so you can check the analog performance of internal circuits. I recently wrote about this topic: http://www.edn.com/article/CA6586230.html

Finally, it is common to use analog techniques to remove normal variation using feedback – the classic case of a PLL where variation in the period or frequency is removed by locking to a reference using a feedback loop.

So the bottomline is that analog on 45 nm (and below) is being successfully designed, it may not be for the “old school of analog designer”. In fact we are in the midst of developing high performance mixed-signal circuits on 28 nm.

In Chicago waiting for my flight home to San Francisco last night, I was chuckling over some email exchanges that I saw on my blackberry between the marketing communications group and our product line managers. It was regarding a campaign to describe the importance of a complete protocol solution for connectivity IP such as USB, PCI Express, SATA and DDR. The idea of the campaign is to use popular icons that work well or go together, as a way of describing the pieces that comprise the complete solution. In our case this is the physical layer, digital controller, verification IP, and in some cases, software drivers.

I like to use the seven layer OSI model when presenting this concept.  The first three layers do a nice job in describing what is needed for the complete connectivity IP solution, going from the transport layer down to the physical layer. Ideally, vendors selling IP focused on a connectivity standard should provide all of these; the goal is to circumvent any interoperability issues between the various layers. Remember you are dealing with an analog/mixed-signal hard macro physical layer interfacing to a configurable digital controller which includes the data link, transport layer, bus interface, and let’s not forget the software drivers. That’s the key to the complete solution. If you need for example, a SATA interface on your chip, the solution must include the physical and the digital layers all tested to ensure interoperability going from the SATA connector all the way to the on-chip system bus.

What about the red-headed step child?

Well, not included in the OSI example I gave, but important in terms of the complete solution is verification IP.  Through techniques such as “directed and constrained random methodologies” the various configurations in the digital layers can be validated including sub-system level verification. I’m certainly not an expert here – you can read all about this in our verification blog.

So, my input t o the campaign: Starsky and Hutch with Huggy Bear.

Getting analog functions on a chip that is mostly digital poses many challenges for the analog designer. Are they equipped? Look at it from the perspective of high speed interfaces that are needed on today’s digital 65- and 40 nm chips, like SERDES or DDR. The “prima donna” analog designers have had the luxury of supply voltages and process technology in their favour. But the bottom-line is can they design with these technologies and still meet performance in terms of tight jitter spec and sufficient link margins?

“As I was walking up the stair I met a man who wasn’t there. He wasn’t there again today.”

Was this man virtual? 

In the computer world, virtualization is a technique for hiding the physical computing resources from the way in which other systems, applications, or end users interact with those resources. This includes making a server or an operating system appear to function as multiple logical resources; or it can include making multiple physical resources (such as storage devices or servers) appear as a single logical resource.

The PCI Express protocol with I/O virtualization allows multiple operating systems running simultaneously within a single computer to share PCI Express devices. From the PCI-SIG website (http://www.pcisig.com/specifications/iov/)  These are grouped into three areas: 

• Address Translation Services (ATS): this specification provides a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O Virtualization.
• Single Root IOV: this specification provides native I/O Virtualization in existing PCI Express topologies where there is a single root complex.
• Multi-Root IOV: this specification builds on the Single Root IOV Specification to provide native I/O Virtualization in new topologies (such as blade servers) where multiple root complexes share a PCI Express hierarchy.

This functionality in the PCI Express protocol will enable network administrators virtualize or share peripherals and endpoints across different CPUs.

Any guesses on the author of the quote?

Well, it was a long summer break, since my last entry! Over the past few months, I spent quite a bit of time with customers around the globe learning about their fabrication technology needs. Here are the trends I’m seeing…

32 nm
- Reduction of product cost and power compared to 45 nm
- Foundry offerings include HKMG
- Migration started, leading IDM’s ramping up initial volumes in Q4/2009
- Ramp-up of 32 nm requires cost per function to be reduced (exception can be processors for high-end servers where price premiums can be maintained)
- Shrink path to 28 nm
- Mainstream market adoption projected in ~2012

45/40 nm
- 1st wave customers designing in 45/40nm
- Major driver: wireless handset/consumer multimedia
- Volumes low due to leakage (parametric yields, soft errors in embedded memory)
Mainstream market adoption in 2010~2011

65 nm
Very fast ramp-up of designs, faster than expected
Use of 65nm for RF as well as digital designs
Very long life cycle projected with Asia moving to 65 nm aggressively and 55 nm being offered in the digital consumer area

SOI
Still remains niche: GPU, CPU, NPU

Would be interesting to read your viewpoints.

I was in discussion with one of our customers about what they saw as challenges of obtaining and integrating analog IP on their 45 and 32 nm chips. Interestingly they were considering to take the analog functionality off the SoC and have a seperate dedicated chip. While there is some rationale behind this, the goal of an analog IP vendor should be to keep abreast of the digital technology roadmap. Looking at our USB 2.0 PHY IP, it can be implemented with 1.8 V devices and meet the USB 2.0 operating voltages (e.g. 3.3V and 5V short tolerance) with good long term reliability in 40 nm. So the bottomline is that through design techniques to accomomdate the higher I/O voltages and understanding the impact of deep sub-micron effects such as STI and NBTI on performance – analog IP such USB 2.0, DDR3 and high speed serdes can be designed on 45 and 32 nm chips.

I’m prompted to write this having read Jim Lipman’s account of the DAC roundtable on “Can IP Integration be an SoC Methodology or is it Always Ad-Hoc?” where I was a panelist. Essentially Jim’s take on the roundtable was that IP integration is not a slam dunk. This is the opposite of what I actually said…Here’s my response to Jim.

My viewpoint is contrary to your summary! What I said at the roundtable was that it is possible for third-party IP integration to be – using your expression – “a turnkey operation”. I said that the dependencies were on the type of IP, completeness of the IP deliverables, thoroughness of the IP design methodology and the expertise of the IP design team. The last two points are not so apparent until you actually engage with the vendor.

Starting with the “type of IP”, I was at pains to highlight the differences of  non-standards based IP such as PLL’s and data converters, stating that  there is no standard spec and the integration deliverables need to be modified depending on SoC interface. This is where you cited the VSIA as being a potential solution and I countered that each of these blocks is application dependant making the job of creating a standard checklist onerous.

Using PCI Express as an example of standards based IP, my point was that even though it is a very complex protocol from the digital link layer to the serdes based PHY, the IP can be designed such that it can be integrated by an engineer that is not an expert in the protocol or in mixed-signal. What a good third party vendor does, in order to make the IP drop-in, is to provide all the design views including detailed integration guidelines. I spoke about the different lane configurations that are supported in PCI Express (x1, x4, x8) and that the IP deliverables must be targeted for these different lane counts.

The methodology used to create the IP deliverables is also very important and at this point we spoke about test-chips, compliance workshops, split lots to see the impact of process shifts on performance and silicon characterization. I added that good IP vendors must also provide support for ESD and latch-up protection.

In terms of the IP design teamÂ’s expertise, the most important criteria is that the IP must be designed like the rest of the (predominantly) digital SoC, in a bulk CMOS technology, no special process options for on-chip inductors, for example. Designers building IP for SoC integration such as a SATA PHY, face different challenges to the designers of discrete SATA chips. I made the assertion that the discrete designer may not necessarily design good IP. Power, area, ease of integration, and production testability are the key care-abouts of the IP designer whereas the discrete designer is focused on performance.

I also said that we cannot control where customers place the IP on their chips, and spoke about the IP design methodology – essentially what we do before we ship IP to customers. At Synopsys our test-chips have noise generators around the IP to ensure robustness in a harsh digital SoC environment.

Making the IP easy to integration is only part of the story. If you now have PCI Express on your chip how do you test it? To this I said that we provide on-chip diagnostics and test vectors that enable our customers to do production testing using a conventional digital tester, eliminating the overhead of writing the test-program.

I concluded by saying that good third party IP vendors have a roadmap aligned to their customerÂ’s future needs, for example at Synopsys we do this by working on the standards bodies like PCI-SIG and USB IF for the next protocols generations and the foundries for the latest technology directions. Today weÂ’re offering a number of very powerful silicon proven IP building blocks and customers now have at their finger tips the ability to build systems-on-chip, the system engineering task is becoming more complex, but also offering more room for differentiation.

IÂ’m very optimistic about the future!
 

A busy week, this week for mixed-signal IP. Leaving for Anaheim early Monday morning for DAC and then returning for PCI-SIG Developer’s Conference later in the week. Just completed the finsihing touches for the tutorial on  “Advanced Methodologies in Validating and Integrating High Speed Serial Interconnects in the Ultra Deep Sub-micron CMOS Era”, presented with Open Silicon on Tuesday afternoon. http://www.dac.com/events/eventdetails.aspx?id=77-144 for details. This is a “strictly for designers” tutorial.

Also during the DAC week you can see a PCIe 2.0 PHY silicon demo at the Common Platform booth, feel free to come over and ask me any questions, I’ll be pleased to show you some of the exciting features like the the built-in diagnostics showing the received eye at 5Gb/s.

Before heading back for the PCI-SIG Developer’s Conference, I’ll be participating on an IP Roundtable Breakfast – Wednesday, 8AM at the Hilton Hotel: “Can IP Integration be an SoC methodology or is it always ad hoc”.

For the PCI-SIG DevCon, we’ll have demo of the PCIe 2.0 PHY and on June 12th will give a talk on: “Designing High Speed Transceivers for PCIe 2.0 and Beyond”

Often appearing in roadmap foils and even a few IP vendors claiming 10 Gb/s serial performance supporting XFI, there now seems to be a stepping stone to these higher speed serial link requirements. RXAUI is essentially two XAUI lanes running at 6.25 Gb/s. Serdes IP integration is a challenge and although integrating mulitple 6.25 Gb/s lanes is not for the faint hearted, it can be done. Today’s 65 nm technologies can reliably meet the speed requirements. RXAUI has made the requirements of highly dense 10GE systems a reality.