Generally speaking the IP market growing quickly at 15% year-on-year and it is projected to be $2.7B by 2010. Outsourcing mixed-signal physical interface IP for the protocols like USB, PCI Express, SATA and DDR2 is becoming commonplace, also we have seen large IDM’s such as TI outsource to fabs such as TSMC. The advanced CMOS processes such as 45/40 nm make developing mixed-signal IP more complex. The challenges are in the lower supply voltages and the DFM patterning requirements impacting analog performance. Data rates are increasing to 5 Gb/s in the next generation SoCs. Customers are demanding more integrated solution (digital, physical, software, verification IP) for these protocols.  The trends we are seeing in mixed-signal physical interfaces are following two vectors. One is the demand for these interfaces to be supported on 45 nm and 40 nm technologies with 1.8 V oxides and the other is higher speeds for these protocols. 

For example the USB roadmap now includes USB 3.0 – this is the next “sexy” USB protocol, 10x the speed of USB 2.0. Tier one customers will want to be one of the first to have it with broad deployment starting in 2010. The 10x speed-up results in 5 Gb/s, in other words you can transfer an HD movie typically about 30 Gbytes in just over a minute compared to 15 minutes using today’s fastest USB. In order to achieve this speed a serdes (serializer/desializer) technology will be implemented with adaptive equalization to support long cable lengths. Backward compatibility will be supported with four additional lines.

Another trend is “going green”, that is, system designers are looking at ways to reduce power and for USB this means “LPM” and “HSIC”. The goal of Link Power Management is to reduce power consumption of USB devices and hosts and potentially extending battery life by at least 20%. HSIC or “high speed interchip USB” is USB without the cable or the connector. It allows low power high-speed data transfers (480 Mbps) using a source synchronous clocked serial interface. Low power is achieved with 1.2 V LVCMOS signalling levels. The backers of this interface include Nokia, Qualcomm, Ericsson Mobile Platforms, Motorola and Intel. The first products tape-outs will be in 2008 with applications that need to support embedded designs and portable devices such as smart phones and mobile internet devices. More about low power later…. 

PCI Express is getting faster with the announcement of the 8 Gb/s PCIe 3.0 (or Gen. 3). Revision 0.9 of the specificaiton is expected first half of 2009 and is targetted to reach products in 2010. Another trend we are seeing is “IOV” – IO virtulization. Essentially, IOV enables a multiple function PCI Express device to virtulize the functions to make it appear that they are not owned by one processor, so they can be used by many processors. The market segments inlude blade servers, storage and networking.