Archive for December, 2007

Whereas scaling of digital circuits is has been investigated in detail, the application of scaling analog circuits is still not that common. For example typical transistor dimensions in an analog circuit are a few multiples larger than 40 nm minimum channels.  

The sub-threshold characteristics of devices with channel lengths below 2 µm are very different to devices with larger dimensions. It has been observed that the current becomes exponentially dependent on drain voltage independent of V_DS . This effect is sometimes referred to as “drain induced barrier lowering” (DIBL). If this effect can be avoided then I_D decreases exponentially as V_GS is reduced below V_T. Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit voltage gain. Scaling dimensions but keeping supply voltage constant, will, however decrease the gain. The dynamic range of analog circuits such op-amps fall because the analog signal range becomes limited due to the reduction in the supply voltage. The problems of scaling down include fabrication challenges, limitations in the design of devices and circuits and the efficiency and distribution of power supplies.

Thermal noise will remain constant because the device transconductance remains constant under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by translating the signal to a higher portion of the frequency spectrum, using chopper stabilization.  

The going green discussion is vogue in the semiconductor industry opening up interesting power saving ideas in integrated circuit design. In the design of mixed-signal IP many factors contribute to the overall consumption of power. This posting opens up a series of articles on the methods available to the designer to reduce power consumption in a circuit. The common methods include: 

• Simplifying the complexity of the circuit
• Taking conventional architectures and converting them into designs that consume less power
• Gearing the integrated circuit technology towards low power performance by using, for instance, high Vt processes
• Decreasing transistor dimensions together with lowering the supply voltage

Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples. (And also because I know a lot about op-amp design!) 

a.      The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, whilst preserving an acceptable bandwidth and slew rate are now required in the single gain stage. 

b.      The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible. 

c.      Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed.  d.      Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45º to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit. There’s a nice write-up in Gray and Meyer. 

e.      Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.   

f.        The basic two-stage differential input op-amp can be designed in the subthreshold current region to minimize the current consumption.  The next posting will describe techniques to save power in high speed serial interfaces both in active and sleep/low-power modes.

Generally speaking the IP market growing quickly at 15% year-on-year and it is projected to be $2.7B by 2010. Outsourcing mixed-signal physical interface IP for the protocols like USB, PCI Express, SATA and DDR2 is becoming commonplace, also we have seen large IDM’s such as TI outsource to fabs such as TSMC. The advanced CMOS processes such as 45/40 nm make developing mixed-signal IP more complex. The challenges are in the lower supply voltages and the DFM patterning requirements impacting analog performance. Data rates are increasing to 5 Gb/s in the next generation SoCs. Customers are demanding more integrated solution (digital, physical, software, verification IP) for these protocols.  The trends we are seeing in mixed-signal physical interfaces are following two vectors. One is the demand for these interfaces to be supported on 45 nm and 40 nm technologies with 1.8 V oxides and the other is higher speeds for these protocols. 

For example the USB roadmap now includes USB 3.0 – this is the next “sexy” USB protocol, 10x the speed of USB 2.0. Tier one customers will want to be one of the first to have it with broad deployment starting in 2010. The 10x speed-up results in 5 Gb/s, in other words you can transfer an HD movie typically about 30 Gbytes in just over a minute compared to 15 minutes using today’s fastest USB. In order to achieve this speed a serdes (serializer/desializer) technology will be implemented with adaptive equalization to support long cable lengths. Backward compatibility will be supported with four additional lines.

Another trend is “going green”, that is, system designers are looking at ways to reduce power and for USB this means “LPM” and “HSIC”. The goal of Link Power Management is to reduce power consumption of USB devices and hosts and potentially extending battery life by at least 20%. HSIC or “high speed interchip USB” is USB without the cable or the connector. It allows low power high-speed data transfers (480 Mbps) using a source synchronous clocked serial interface. Low power is achieved with 1.2 V LVCMOS signalling levels. The backers of this interface include Nokia, Qualcomm, Ericsson Mobile Platforms, Motorola and Intel. The first products tape-outs will be in 2008 with applications that need to support embedded designs and portable devices such as smart phones and mobile internet devices. More about low power later…. 

PCI Express is getting faster with the announcement of the 8 Gb/s PCIe 3.0 (or Gen. 3). Revision 0.9 of the specificaiton is expected first half of 2009 and is targetted to reach products in 2010. Another trend we are seeing is “IOV” – IO virtulization. Essentially, IOV enables a multiple function PCI Express device to virtulize the functions to make it appear that they are not owned by one processor, so they can be used by many processors. The market segments inlude blade servers, storage and networking.