I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever! Ten years of mixed-signal IP
Posted by Navraj Nandra on November 27th, 2007
Design and Reuse is celebrating it’s 10th anniversary with a number of forums and panels during the IP 07 Conference in Grenoble. Mixed-signal will be represented on the panel: A Decade in Library IP and Mixed Analog IPs (Dec. 5, 15:15-16:10). This is an opportune moment to both reflect and to gaze into the future with respect to analog IP. I would be interested in you sharing opinions and ideas to start a discussion on the following:
What has been the most important development in the analog IP industry in the past decade?
What do you believe will be the most significant challenge facing the analog IP industry in the coming decade?
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Hi Navraj,
1) 1997 – 2007:
- Silicon qualified accurate analog device models from foundries
- Silicon qualified block level designs from IP providers provided
through foundries, targeting specific foundry
- Specialized IP provider companies
- Foundry RF-component cell layouts and models qualified with
s-parameter measurements
- PDK releases for foundry technologies
- Minimizing technology timeline diversity going from logic design
capability to completely characterized process for analog development
2) 2007 – 2017:
- Quality of IP enforcement through industry standard practice for
qualification process
- Open source modifiable PDK releases from foundries
- Configurable analog IP (SW,HW)
- Top level/System level simulation models for analog IP
- Analog IP testability in design (registers, probes,layout options,
fuses, OTP-options) agreement for standard practice
- Migratable analog IP between foundries and technology nodes
- Accurate IP documentation
- Minimizing technology timeline diversity going from logic design
capability to completely characterized process for analog development
(still continues to be a challenge to get analog IP fast onto SOC on new
process node)
Best Rgds,
Pekka
Grenoble in December, not unlike a metaphorical visit to hell. I went to IPSOC two years ago, and got to experience 33-34F degree weather, and rain the whole week. Hopefully you will have better weather.
1) what has been the most important development in the library and
analog IP industry in the past decade (since 1997)?
1) Quality, which means well documented design practices.
2) what do you believe will be the most significant challenge to the
library and analog IP industry in the coming decade (until 2017)?
2) Feature Size and power supply headroom, leakage, DFM patterning. To get real SOC’s more analog content will be added to the chip. Some of this will be DSP in nature, but significant amounts will be analog. Using statistical timing tools for digital in place of running 40-50 process corners is great; analog will still require all those process corners. As feature size goes down, the core transistors operate with lower voltage which means less headroom. Less headroom means more noise; not a good trait in a analog circuit. Analog by its very nature is “leaky,” but making sure it’s not too “leaky” will be a challege. Can matching be guaranteed with DFM enhancements required to get good litho yield?
Hopefully my perspective is of some use. Good luck on you’re trip.
Hi Navraj,
To answer your questions:
1) 15 years ago we did all libraries (analog and digital core and IO) ourselves. The quality and performance of digital libraries is now excellent and makes own development redundant. A large amount of analog libraries was made available for the big foundries such as TSMC, Chartered, UMC, …
We could make complex chips and concentrate our effort in the system definition and the optimisation of the chip performance based on off-the-shelf libraries.
2) The number of foundries and process technologies decreases which makes it easier for the IP industry. The challenge probably is the complexity of new process technologies. Making high performance analog with below 45nm process nodes will be the biggest challenge.
Enjoy the conference!
Mario
Dear Navraj,
Sorry but I do not have much time to think in detail obout the topic. But at least I can share a view “provocative” thoughts about it:
1)
In 1997, everyone believed that there will be an IP industry created and fast crowing. In reality this was not the case. Except of ARM, no important player could create a profitable business. Many old players (e.g. Aspec, Artisan) and new players (you remember Barcelona!) disappeared.
ARM won because they were very successfully driving a standard in the phone industry comparible with Microsoft in PC. In that sense even ARM is not an IP company.
2)
The challange for analog is standardization. W/o standardization analop IP will continue to suffer to become a real industry. An important part of standardization would be semiconductor processes. Today the largest foundry set the process standard for logic processes. There is no standard for any analog process. Therefore, for the time being, analog IP will be provided by the analog foundries, EDA industry and many small, very specialized analop IP companies.
Best regards,
Dr. Jens Kosch
Chief Technical Officer
Navraj,
My ansewers are in line below.
On Sun, 25 Nov 2007, Navraj Nandra wrote:
>Date: Sun, 25 Nov 2007 16:01:29 -0800
>From: Navraj Nandra
>To: vincent.vonkaenel@ieee.org
>Subject: Analog IP perspectives
>
> Hello Vincent,
>
> I hope you had a good Thanksgiving.
>
> I’m giving a panel on analog IP at the IP SOC conference in Grenoble
> and would like to get the following perspectives:
>
> 1) what has been the most important development in the library and
> analog IP industry in the past decade (since 1997)?
I think this is the availablity of complex analog IP like high speed serdes, high resolution A/D, high speed D/A from various vendors.
> 2) what do you believe will be the most significant challenge to the
> library and analog IP industry in the coming decade (until 2017)?
>
Make the IP available for various process and process options (like metal
stacks) early enough that early, high leverage companies can benefit from
IP available.
Vincent