A wide range of wireless SoCs supporting near field communication (NFC), Bluetooth, 802.11, and other radio applications can reduce both system power and cost by integrating multiple time programmable (MTP) non-volatile memory (NVM) on-chip. The MTP NVM can be used for field updatable lookup tables (for routing NFC packets), device matching (in the case of Bluetooth), customer settings (i.e., volume or radio pre-sets), or general configuration and calibration data.

While embedded MTP has been easily scalable from 350-nm to 65-nm, developing embedded MTP NVM in a standard CMOS process is becoming more difficult as the technology moves to more advanced nodes.

Embedded MTP is typically developed on the concept of storing charge on a floating gate. As the I/O voltage and corresponding gate oxide thickness reduces in advanced process nodes, the intrinsic ability of the process to store charge approaches the theoretical limit. Based on the work of Ielmini et. al1, in order to achieve 10-year data retention, the gate oxide needs to be above 44 angstrom, which falls between the typical gate oxide thickness for a 1.8V and a 2.5V transistor. Traditional embedded flash or embedded EEPROM technology normally requires additional processing which not only adds cost to the manufacturing process but may impact the device performance and may require design modifications to maintain the wireless or RF performance of the SoC. Synopsys’ DesignWare NVM IP addresses both the cost and design drawbacks by developing the IP in standard CMOS processes with no additional masks or processing steps. DesignWare IP has the added advantage of operating solely from the 1.1V supply, with all the necessary high voltage and support circuitry integrated in the NVM block itself.

Synopsys developed MTP in standard CMOS processes starting at 350-nm and now has silicon-proven embedded MTP in an industry leading 40-nm low power process. One of the key challenges in developing MTP in advanced process technologies is managing the stress put on the gate oxide during program and erase operations. At 40-nm, the most common I/O voltage has been reduced to 2.5V, and the gate oxide for these transistors is in the range of 50A. Reliably programming and erasing thousands of times requires a great deal of care and expertise. As I’ve mentioned before, Synopsys has the most thorough and comprehensive characterization and qualification methodology of any embedded NVM IP supplier. Already licensed to multiple customers targeting consumer and industrial wireless applications, Synopsys’ 40-nm embedded MTP is in the process of completing qualification testing and will be generally available within the next few months.

The Ethernet Technology Summit, April 2nd to 4th at the Santa Clara Marriot in San Jose, focuses on the use of Ethernet throughout the networking space. This includes the emergence of 10-Gigabit Ethernet as a key LAN technology on the desktop and in data centers. I will be addressing the requirements of including 10G IP on a networking chip.

The summit also covers the emerging standards for 40-Gigabit and 100-Gigabit Ethernet. It also includes the use of Ethernet as a carrier backbone and transport method, as well as in storage applications and in virtualized data centers and clouds. Other topics of interest include design and development, fabrics, chipsets and components, security, delay and packet loss, convergence, big data, and market research. .

As the most common LAN technology, Ethernet is widely used and understood. Standards are managed through IEEE (IEEE 802), and work on new standards proceeds continously. Chips, parts, boards (particularly network interface cards or NICs), and expertise are all widely available. The Ethernet ecosystem is large and has many significant players, such as Cisco Systems, Intel, Broadcom, Marvell, Alcatel-Lucent, Hewlett-Packard, and Ericsson. Trade groups such as the Ethernet Alliance and MEF are very active and promote education, testing, and certification.

Challenges facing ethernet: Need for higher speed with 100-Gigabit Ethernet on the horizon, need for management, quality assurance, and security tools as Ethernet moves into service provider networks, reducing power usage, increasing bandwidth, and the need for software to handle storage-over-Ethernet and new approaches such as convergence and Fibre Channel over Ethernet.

Major Issues covered during the conference include: Higher speed, higher effective bandwidth, lower power consumption, quality-of-service, security, management tools, test equipment, certification and convergence.

Key notes include: “Welcome to the Generation of Open Ethernet” by Eyal Waldman CEO Mellanox, “Ethernet’s Next Step: 400 Gigabit” by John D’Ambrosia, Chairman Ethernet Alliance, “The Next 40 Years of Ethernet” by Jane Li COO Huawei Enterprise US, “Unified Data Center for the Cloud Era” by David Yen, Senior VP/GM Cisco.

Embedded Vision is a hot application these days. For those of you who have kids, you may have experienced already a lot of it from the gesture recognition area with the Kinect box. Samsung’s Galaxy S4 sports a camera that detects your finger pointing in the air to steer the user interface. And sooner than you expect your car will automatically break if you don’t notice the pedestrian crossing the street. What do all of these applications have in common? All of them have a camera sensor that is followed by sophisticated, real-time image processing that extracts the information that is relevant for the application.

In many cases for example (the pedestrian is a good case for that) it is sufficient to detect the edges of an object in the first place. I had the chance to experience my own edges recently as I walked up to an embedded vision processor demonstration on the 2013 SNUG Design Community Expo show floor this week. My body contour showed up as a spider web of white lines on the monitor in real-time as I was moving in front of the camera screen. What I actually saw was a specialized processor designed with a nifty tool, Synopsys Processor Designer. The embedded vision processor had been implemented on a HAPS(r) prototyping system that also had the daughter card with the HDMI outputs driving the screen and the AVI input from the camera. I was told that my image could be slightly improved by fine tuning the algorithm parameters, but from an edge detection perspective I was looking just fine….

Ok. So now I’ve got your attention SNUG is where you will find all these and more!

Next Monday, Tuesday and Wednesday is our annual SNUG (Synopsys Users’ Group) at the Santa Clara Convention Center. Registration closes tomorrow noon-time (Thursday March 21st at 12PM – see registration link at the end of the post).

Monday will feature the IP Summit, comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries presented by Verisilicon and Imagination; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. Both days will provide ample opportunity to learn formally through tutorials, panels and presentations from customers and our R&D team on FinFET technology; and, informally through networking opportunities.

On Wednesday morning, my good friend and colleague, Dr. Yervant Zorian will deliver a tutorial on “Embedded Memory Test, Repair & Diagnostics”. He will address the very interesting topic facing SoC developers today, that yield relies heavily on memory yield. There is greater manufacturing complexity in 20-nm and FinFET technology nodes, which create new yield challenges, both in the form of increased defect densities and in the form of new types of failure mechanisms that need to be modeled for accurate detection, diagnosis, and repair. So, it is essential to have an embedded memory test and repair solution that not only meets the above challenges for today’s designs, especially those at 20-nm and below, but that is also cost-effective. Yervant will include a description of a new hierarchical embedded memory test and repair architecture, resulting in a 30% area reduction compared to the previous generation, support for high performance processor cores and advanced test, repair and diagnostics algorithms that target designs on advanced planar and FinFET technology nodes.

Oh, yes the beer and race track. Here are the details:

Where: SNUG Pub – The largest pub in silicon valley
When: Tuesday, March 26, 4:45 – 7:00 PM
What: SNUG Pub Grand Prix, you will be able to see our involvement in the automotive industry and will be able to test your driving skills and compete at the “SNUG Pub Grand Prix” at the Micro -Reality Race Track or the Daytona II Racing Simulators from 4:45 to 7:00 pm. It will be a great way to relax and have fun!

And…Yervant and I like beer and we love discussing what we do, so looking forward to seeing you next week.

SNUG registration closes tomorrow noon. Please visit www.synopsys.com and follow the links.

SNUG Pub - The largest pub is silicon valley - I know I've been to most of them!

SNUG Pub Racetrack

The MIPI M-PHY was developed for mobile devices where the important requirements were low pin count combined with very good power efficiency and high electro-migration interference (EMI) immunity. High performance is achieved through “gears”.

Gear 1 at 1.45 Gbps per lane, Gear 2 at 2.9 Gbps per lane and Gear 3 at 5.8 Gbps/lane. Mobile devices can be sensitive to EMI, and each gear of the M-PHY has two frequencies that are close together allowing to select the optimum from an radio receiver sensitivity perspective. Depending on your bandwidth needs you can go up to eight lanes. The picture below shows the M-PHY, it supports a number of protocols for different applications such as camera serial interfaces to camera sensors, internal displays, USB 3.0 or PCI Express protocols for chip to chip interfacing. For embedded storage, the next generation after the embedded multi-media card (eMMC) will be universal flash storage (UFS), a protocol the overlays the M-PHY.

MIPI M-PHY supporting many protocols for popular mobile requirements

So the point is that there are many applications and protocols that will use the MIPI M-PHY and the bandwidth needs are increasing. The latest specification to support the emerging bandwidth needs is Gear 3. This week during the MIPI Alliance face-to-face meeting in Asia, we will be demonstrating the first silicon proven M-PHY operating at High Speed Gear3.

We will be hosting our annual Synopsys user’s group meeting (SNUG) in Santa Clara this month. We will feature an IP Summit comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. You can register on
http://www.synopsys.com/IP/Pages/ipsummit2013.aspx
These tutorials provide insights into today’s IP development challenges and what may impact your design thinking in the future, propose solutions; presented by industry experts and this event will also provide a unique networking opportunity with IP developers, SOC design architects and system engineers.

I’m in the process of completing a tutorial “20-nm Mixed-Signal IP – A Stepping Stone to 16-nm FinFET?” (presented on Monday March 25th) I’m coming to the following conclusions, would be great to get your opinions too! Looking forward to seeing you.

1. Power, performance and area drives IP specifications for the analog/mixed-signal designer, these are achieved through architectural or schematic level design changes in advanced planar and FinFET designs

2. Analog process qualification vehicles are necessary to provide insight into the impact of the early design rules and process parameters on performance

3. FEOL impacts FinFET processes; key learning (stepping stone) from planar is DPT and device quantization

4. FinFET impacts analog parameters; completely new layout structures needed

5. Engineers will leverage FinFET physical properties and invent new circuits

You can register on http://www.synopsys.com/IP/Pages/ipsummit2013.aspx

Word has it that 14-nm or 16-nm fInFET processes are based on a planar CMOS 20-nm “back-end-of-line”. We’ll get into what back-end-of-line means in a later blog post. For now consider what the first statement implies since it is touted in the industry as a “fast and low risk ramp to finFET’s”, that the expertise developed for a 20-nm analog/mixed-signal IP design could be leveraged. But is this really be true? And is this the right question? IP reuse is about time to market, however, what an analog/mixed-signal designer really cares about is to get performance by the realization of higher fT and fmax, achieved by higher transconductance, output resistance, low gate capacitance and resistance. Nothing new here – this is our daily job as analog designers. The consumer of the IP, in many cases the SoC architect not only cares about time to market but also power, performance and area. Plus the IP must work on the first instantiation. The last two points are opening up new design possibilities for the analog designer. Going back thirty years, the initial CMOS circuits were based on the bipolar equivalents but over time new techniques such switched capacitor circuits started to appear as analog designers started to exploit the property of MOSFETS. We are at the same juncture with finFET’s.

The interconnects and dual pattern technology are similar to planar technologies but the devices are very different. In March, I will talking in more detail on this topic at SNUG San Jose. Going into how 20-nm planar designs require a much deeper link between layout and power, performance and area requirements compared to previous nodes. Furthermore, quantization of these devices means that the 20-nm planar development is from the ground up, so you can’t reuse even at the 28-nm node. I’ll be providing design examples and will let you determine whether 20-nm is truly a stepping stone to finFET’s.

Regardless, this is an exciting time to be analog/mixed-signal designer!

As many of my readers have experienced, getting your first silicon in the lab can be an exciting albeit nervous moment. In this post I am showing 20-nm silicon results – eye diagrams with excellent performance of some of the popular interface IP’s such as USB, PCI Express and MIPI. These all came up working first time on 20-nm in our characterisation labs. My engineering team did not leave anything to chance to ensure right first time results.

Let’s first look at the 20-nm process. The impact of this process on physical IP s had both challenges and benefits. The benefits included higher transition frequency (fT) and more transconductance (gm) of the transistor that enable faster designs with more gain. We also took the opportunity to re-design architectures to improve on power, performance and area at 20-nm. The challenges included new layout requirements that involve supporting double patterning technology (DPT), density requirements for metal and polysilicon, lower transistor output conductance (gd).

So how did we get it right? In order to ensure right first time silicon success, we developed an advanced silicon test-chip design methodology which solved two fundamental challenges of enabling 20-nm ready physical IP. The first is related to the CAD flow: the verification decks for design rule checking, metal filling, restricted density design rules below metal one, required significant changes to the infrastructure and management of the design database compared to 28-nm. The goal using this methodology is to prepare a 20-nm “pipe-cleaner” enabling faster design of the complex physical IP.

Due to aggressive time to market schedules, customers expected guarantees that physical IP blocks work on the first instantiation.  This necessitated correlation between SPICE simulations and silicon characterization data of the fundamental IP building blocks such as transistors, capacitors and resistors of various aspect ratios. This is the second, and larger, challenge that is addressed in a test-chip before we develop the IP. This activity is only possible through deep collaboration with the foundry.

In the test-chip, a statistically meaningful number of devices was chosen to ensure the simulation to silicon correlation, this equated to 1500 devices with different layouts and density dependencies providing data for resistor / transistor matching and metal mismatch due to DPT. Ring oscillators and operational amplifiers gave early insight into the gate delay and analog performance of the 20-nm process. Metal-in-Metal (MiM) capacitor structures are also used. The methodology includes overstressing devices to evaluate the impact on reliability due to NBTI, PBTI and HCI. Electro-static discharge (ESD) structures are part of the physical IP and these needed to be designed for HBM and CDM performance – for example CDM must be tested across different voltage domains. In order achieve USB 2.0 compliance the 20-nm I/O need to support 5 V and these structures must also be implemented.

A current-to-voltage voltage converter for measuring the devices with better than 0.5% accuracy acts as the on-chip instrumentation and this is more than adequate for devices that typically have greater than 20% mis-match. A 4-pin JTAG interface allows full visibility and the 1500 devices can be tested in under two minutes.

So it came down to an advanced test chip methodology even before we started developing the interface IP and highly experienced analog/mixed-signal engineers to absorb, virtually in real-time, the PDK updates and to assess the impact on the designs.

Synopsys Announces Energy Efficient 28-nm PCI Express 3.0 PHY with Support for 10GBASE-KR

I am thrilled to share that this morning we announced our Enterprise 10G SerDes IP in leading 28-nm process nodes to address the connectivity needs of a broad range of networking and computing applications. This announcement has been welcomed by our customer base that has been asking for an IP vendor to provide 8G/10G SerDes solution. So how is this different from the other PCIe 3.0 and 10G Ethernet solutions on the market? Let me summarize in the following 7 key points:

1. Practicing Perfectionism: Enterprise 10G SerDes is a multi-protocol, multi-rate solution that spans from 1.25Gbps to 10.3Gbps and supports key protocols including PCIe 3.0, 10GBASE-KR, OIF CEI-6G-SR, SGMII and QSGMII. The architecture is built on our 10+ years of SerDes leadership and leverages Synopsys’ strong 28-nm experience (100+ design wins) to provide a stable, high-quality solution with very competitive area, power and performance specifications. Special attention is paid to manufacturability, yield, and other complex issues like ESD at 8G/10G data rates.
2. Energy Efficiency: Our years of leadership in various consumer applications has been leveraged to reduce both active and leakage power to facilitate green enterprise technologies. We also support advanced PCIe power down modes and IEEE’s Energy-Efficient Ethernet (EEE) standard to future-proof our offering for years to come.
3. Engagement Model: Complex high-speed SerDes IP inherently comes with intricate integration challenges that include signal integrity modeling and package design. We have been able to overcome these challenges through close collaboration with our lead customers, helping them successfully integrate the high-speed SerDes into their high-density ASICs for extremely high data throughput without compromising key power, area or speed goals.
4. Complete Solution: This message has been re-iterated many times before, but never has it been so important. The Enterprise 10G SerDes is part of Synopsys’ complete PCIe 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. This is especially important given the delays and vagueness around the PCIe PIPE 3.0 specification. In fact, Synopsys was the first and is perhaps the ONLY company with a complete PCIe 3.0 solution that achieved PCIe FYI compliance.
5. Focused Protocols: Consistent with our ideology, we continue to support a limited number of the most popular protocols with 100% commitment to the highest quality and lowest risk. As Bill Cosby said, “I don’t know the key to success, but the key to failure is trying to please everybody.”
6. Support for High-End Consumer Applications: The SerDes is architected to support high-end consumer battery-powered applications, including support for L1 sub-states and wirebond packages.
7. Commitment: Synopsys is committed to the Enterprise SerDes product line with a well-defined roadmap to scale data rates from 10G  to 12.5G to 16G to 28G in leading FinFET technologies. We are engaged in advanced discussions with prominent enterprise players to address their ongoing concerns, including:

• The last mile
• Insatiable demand for bandwidth
• Peak hour demand
• Flooded networks
• Guarantee of service
• Explosion of Internet bandwidth

Modern PHYs include transmitters which implement multi-tap FIR filters (e.g. three taps for PCIe3) and receivers which typically implement both linear equalizers and DFEs. The purpose of all of this equalization capability is to compensate for the frequency dependent attenuation of the channel.

 An example of a channel is shown in the figure above.  A transmitted data signal passing through this channel will experience a different amount of attenuation depending on its frequency content. To understand how signals contain different frequency content we can consider four examples of forty bit data patterns shown in the figure below.

 The data pattern at the top left contains alternating 1010 data, which is the data pattern which has the highest frequency content possible (Note: this is known as Nyquist data). For the case of PCIe3, the frequency content of this signal is 4GHz. (Note: As the signal is shown as a square wave it is actually composed of many frequency components, however this serves as a first order approximation.)  The data pattern at the top right has an alternating 11110000…. pattern, which has a lower frequency content compared with the Nyquist data. The data pattern at the lower left has 20 ’0′s followed by 20 ’1′s, which represents the signal with the lowest frequency content we can get with a 40 bit pattern. The data pattern at the lower right is a combination of the lowest frequency data pattern with a lone bit placed in the middle of the low-frequency part of the signal. This combination of low frequency and high frequency content is a challenging pattern, as will be seen. The signals at the output of the channel with a 1V TX launch amplitude are shown below.

Looking at the frequency response of the channel one would expect a large amount of attenuation at high frequency, and indeed looking at the top left eye for the Nyquist data pattern the resulting eye opening at the output of the channel is relatively small. For the eyes at the top right and bottom left it can be seen that lower frequency content results in the large signal amplitude at the top and bottom of the eye, and the eye openings are larger than they were for the Nyquist pattern. At the bottom right we see that the resulting eye opening for lone bit pattern is very small (the small oval at the centre of the eye diagram), much smaller than the eye opening for even the Nyquist pattern.  The effect where different data patterns result in different resulting signal amplitudes (hence different eye diagrams) is known as Inter-Symbol Interference (ISI).

For each of the eye diagrams above well defined trajectories can be seen. The reason for this is that in these data patterns there are only a small number of data patterns, and each data pattern will result in a particular trajectory. However in a random data pattern an almost infinite number of data patterns are present, hence an almost infinite number of trajectories, and these act to essentially fill in the spaces in the eye diagrams shown above. The resulting eye diagram for a random data pattern is shown below.

 An ideal equalizer would perfectly compensate for the frequency dependent attenuation in the channel. If the transfer function of the equalizer was the exact inverse of the channel then the resulting bandwidth of the channel + equalizer would be flat, and thus there would be no ISI. Unfortunately it is not possible to make an ideal equalizer, and hence one is not able to perfectly equalize the channel.

Putting the signal from the above diagram through a simple linear equalizer significantly improve the eye opening, as shown below.

The ISI that remains after equalization is known as residual ISI. The thickness of the fuzz is an indication of how well the equalizer is able to equalize the channel. As the equalization improves, the amount of residual ISI decreases, and when looking at the resulting eye diagram what will be seen is a reduction in the thickness of the fuzz.

For PHYs which operate at high data rates (e.g. PCIe3, 10GBASEKR, CEI11 and above) adaptive equalizers are needed in order to be able to compensate for a wide variety of channels. Adaptive equalizers have many different settings, and in order to select the right one there needs to be some measure of how well a particular equalization setting works. Measuring the thickness of the fuzz is one such figure of merit which can be used to quantify the performance of the equalizer.