BLOGS & FORUMS
The Eyes Have It
|The Eyes Have It|
This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.
I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!
- Navraj Nandra
Posted by Navraj Nandra on January 22nd, 2016
Waiting for my flight from Tokyo to San Jose, I had a few minutes to think about the recent requirements for storage in mobile devices (think SELFIE), the increase in flash memory capacity using 3D technology and the most advanced memory protocol for flash. First, to set the scene, a quick re-cap on memory hierarchy. SRAM is integrated into the microprocessor for cache; DRAM is used for main memory; disk drives and NAND-based solid-state storage drives (SSDs) are being used storage. I’m referring to the latter – the NAND memories used in SSDs.
A bit like Tokyo where I have been for the last week, when you’re out of space, the only way to build is up. Using 3D stacked technology, NAND triples its capacity. It is reported that standard consumer SSDs will increase up to an astounding 10TB of storage. The idea is to stack flash cells vertically in 32 layers to achieve a 256 Gbit multilevel cell (MLC) or 384 Gbit triple-level cell (TLC) die that fit within a standard package. So in moving from NAND to 3D NAND we get lots more capacity.
Published five years ago, Universal Flash Storage (UFS) was designed to be the most advanced specification for both embedded and removable Flash memory-based storage in mobile devices such as smartphones and tablets – effectively replacing SD and eMMC. Shortly afterwards my team announced: “Synopsys Extends Mobile Storage Leadership with UFS and MIPI Alliance UniPro Controller IP” http://news.synopsys.com/index.php?item=123422
So, connecting the three dots: mobile, storage and protocol, last month SK Hynix announced the “World’s First 3D NAND based Mobile storage solution” https://www.skhynix.com/eng/product/nandUFS.jsp
The really exciting part for me is that this product uses Synopsys’ UFS IP solution.
As said by J. W. Park Senior Engineer, SK Hynix “We needed help to quickly deliver a high-performance and power-efficient UFS 2.0 solution for mobile devices. By using Synopsys’ DesignWare UFS, UniPro and M-PHY IP, optimized for power and performance, we were able to integrate the IP in two weeks, speed our design schedule by six months and achieve volume production.”
The vision for we had for high performance storage protocol IP five years ago, has today enabled SK-Hynix to deliver the first 3D NAND for mobile devices.
Posted in General - mixed-signal IP | No Comments »
Posted by Navraj Nandra on September 9th, 2015
Next Thursday, September 17th is TSMC’s ecosystem forum event (OIP – Open Innovation Platform) bringing together the EDA, IP and SoC community to present and discuss solutions to today’s design challenges. http://www.tsmc.com/english/newsEvents/events.htm
This year, I will talk about the concept of “IP subsystems”. Below is the abstract of my talk.
The vision of IP subsystems is now a reality with the ability to integrate specific IP blocks, efficient processors and software into a single subsystem targeting a certain application or protocol. A key design requirement of the subsystem is the ability to support SoC derivatives in multiple process variants such as 16FFC or 28HPC/HPC+. In addition, the components of the IP subsystems including interface, analog, processor and foundation IP must meet the design requirements of the target application. The ability to configure the IP subsystem to the application, while ensuring no adverse interaction, signal and power integrity issues exists between the IP blocks is critical. This has a significant influence on the IP design intent and methodology. This presentation will cover the specification, design, integration and qualificationn challenges and solutions for implementation of IP subsystems for IoT/wearables and automotive applications.
For wearables, the IP subsystem must be designed to work with minimal battery drain, be very low cost, support a rapid wake-up time, and have a consistent power management scheme that supports operation down to 0.6 V, and if necessary, overdrive. The design challenges include meeting protocol requirements, since the signaling amplitude for the USB, DDR and PCI Express interfaces are higher than the core voltrage, and latency. To address this challenge, TSMC offers extended Vt options that allow mixed-mode architectures to solve some of the challenges.
Automotive grade IP means that the IP meets stringent quality and functional safety standards like ASIL B and AEC Q100 combined with temperature profiles defined in Grade 0, 1 or 2, going up to 150C. Meeting these rquirements bring challenges to both the semiconductor technology and IP design and qualification. The SoC’s supporting the next-generation advanced driver driver assistance systems will be manufactured in 16FFC, requiring close cooperation with TSMC and the IP vendor to handle issues such as hot carrier injection, electromigration and NBTI.
By using two distinctly different examples (IoT/wearables and automotive), this presentation will cover the IP subsystem requirements from specifcation, design, integration and application challenges to foundry cooperation.
Posted in General - mixed-signal IP, Uncategorized | Comments Off
Posted by Navraj Nandra on July 16th, 2015
Bluetooth has become the standard wireless interface for mobile devices like wearables, health monitors; it is also implemented in smart home and industrial applications. The requirement is to integrate the radio on your chip and because it’s a standard, you can think of it as IP. Wireless IP.
Some months ago, I was given the task finding and adding this technology to our DesignWare IP portfolio – adding a wireless interface to our broad portfolio of wired interfaces like USB. Today we announced the availability of silicon-proven Bluetooth Smart radio IP that implements the Bluetooth 4.0, 4.1 and 4.2 low energy standards. This is sub one-volt design!
Bluetooth has been around for more than 20 years. The recent breakthroughs included version 4.0, also known as Bluetooth Smart that enabled the technology to be powered from a coin battery cell. In December 2014, version 4.2 went all out to support IoT.
So what are we planning to do with this technology?
Well, the block diagram below, hopefully gives you a glimpse of where we are going with this technology.
Like the Dane king Harald Blåtand (English translation Bluetooth) that united Denmark, Synopsys is uniting a number of IP’s with the ARC processor and Security to deliver on the IoT roadmap.
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Posted by Navraj Nandra on April 16th, 2015
In keeping with 50 years of Moore’s Law, this post is about the results we have obtained for 7-nm FinFET’s and 5-nm nano-wire standard cell logic libraries. These transistors are very new. Trade-offs are being made by Synopsys’ device physicists in terms of electrostatics, leakage, patterning, manufacturability and transistor performance. Before I go any further I should explain that although I work in our IP team, I get to see the exciting work our TCAD (technology computer aided design) team does in developing the fundamental devices used in the IP like standard cells, USB, SERDES and DDR.
What’s even more exciting is that their work on quantum effects at these nodes impacts the FinFET or nano-wire device design – fin width, fin height, different materials (for spacers, channels etc.) – generally anything that can impact the bandgap. Once the transistor or nano-wire properties are defined, a standard cell library can be prepared to see power:performance trade-off in terms of energy versus delay. This feedback can then be applied back to the device engineers.
Using an 11-stage ring oscillators of the 2-input NAND library you can see the spread in performance vs power consumption in the figure below. The switching delay and the energy consumption per switch are shown per one ring oscillator stage, which is a 2-input NAND library cell for three different power supply voltages of 0.5 V, 0.6 V, and 0.7 V. Five 7-nm FinFET and two nano-wire devices were used in the standard cell library experiement.
The 5-nm nanowire’s 3.6X speed and 5X energy advantage applies to 7nm FinFET with nitride or 7nm GeSOI FinFET. The 7nm FinFET with low-k or oxide spacers also looks really good with 2.2X speed advantage and less than half the leakage of the classical 7nm FinFET with nitride spacers.
What we have seen is that the 7-nm FinFET is 2.6x faster with 24% switching energy reduction. The 5-nm nanowire is really fast (3.6x over Si) and really low power (5x less energy). The 5-nm vertical nano wire specific architecture is better than the classically scaled 7-nm FinFET with standard Nitride spacer
The point being made is that there is no apparent reason why technology scaling cannot extend down to 5-nm bringing with it improvements in performance and lower power consumption.
So bring it on, Moore!
Posted in An analog designer speaks!, General - mixed-signal IP, Logic Libraries, PCI Express, USB | Comments Off
Posted by Navraj Nandra on June 2nd, 2014
For this post, I’m stepping out of the world of analog/mixed-signal IP to look at some of the challenges faced by the SoC (system on chip) developers when they are using IP. Firstly, the software content is increasing – in some cases almost half of the development budget of an SoC is spent on software development. Secondly, more IP blocks, both PHY and link layer are required on the SoC. Today these are also pushing the speed envelope to 16 Gb/s for PCI Express Gen. 4 or DDR type memory interfaces running at 3200 Mb/s. Lastly, in order to ensure success of the IP on the SoC and also differentiate the IP, SoC developers are requesting integration services customized to their environment.
It is all about accelerating the time to market by reducing the development time, ensuring correctly working IP blocks from PHY, to link layer, to firmware.
In order to address these challenges, Synopsys today announced the “IP Accelerated Initiative”. At a high level this initiative is comprised of the following (referring to the block diagram below):
- IP prototyping kits that allow you to validate the IP in the exact configuration you want.
Reference implementation of the IP, that is based on HAP’s FPGA system with a PHY daughter card and this allows you to physical connect your USB for example through a cable to the device like a disk drive. This allows you to really exercise the system with the actually IP. But only part of the story, you can only validate hardware in the presence of software – like software drivers that make the hardware actually do something. In order to do this the prototyping kit comes with a 32 bit processor running linux which allows you to develop the drivers and middleware. There is a fast iteration flow which is an automated methodology that allows you to go through the complete IP configuration space, create the exact configuration of the IP for your SoC and then you can download the bit-file representation directly onto the FPGA and this allows you validate the IP configuration in your system. The video shown here describes the implementation.
- IP software development kits allows you to develop software that depends on that IP.
This uses a concept of virtual prototyping – this provides a virtual “target” to software developers, target is the term that software engineers use, so the software development can be done without the need of the actual hardware. To make this task efficient – or to accelerate it – the software development kit comes with reference drivers, a ported operating system. So the point is that the engineer can focus their task on software development rather than on putting the whole environment together. The video shown here provides an interesting demo of this flow.
- Configuration and integration of IP to meet you specific implementation
We support customers through their unique SoC integration tasks that can include clock tree distribution, reset, power management, special side-band signals and test circuits. Since the SOC’s are getting very complex we can provide on-site support in terms of the customization, configuration and integration of the IP.
Addressing SoC Developers’ IP Challenges - It’s Not Just About the IP
The IP Accelerated initiative pulls together all the facets required to get the IP working and validated, allowing the SoC developers to focus on their actual tasks of chip design.
Posted in General - mixed-signal IP | Comments Off
Posted by Navraj Nandra on April 22nd, 2014
Last week at VLSI Test Symposium (VTS) 2014, Synopsys presented “Fault Modeling and Test Algorithm Creation Strategy for FinFET-Based Memories” to a packed room of attendees with several standing, all interested in learning about memory Test for FinFET.
FinFET transistors are playing an important role in advanced process technology nodes. Embedded memories based on FinFET transistors lead to new types of defects requiring new embedded test and repair solution. Due to the special structure of FinFET transistors, the existing fault models and detection techniques based on planar transistors are not enough to cover FinFET defects.
Synopsys has developed a new approach for investigation of FinFET-specific faults. In addition to fault modeling, a new methodology was also developed for test algorithm synthesis. The methodology has been validated on several real FinFET-based embedded memory technologies. Moreover, new faults have been identified that are specific only to FinFETs.
DesignWare® STAR Memory System, Synopsys' memory test, repair and diagnostics solution,
At Synopsys we’re very fortunate to work with Yervant Zorian and Samvel Shoukourian - the industry experts in semiconductor test. From 2000 to 2013, Yervant and Samvel worked on numerous publications and patents on testing of electronic devices and systems—particularly comprehensive embedded test, repair and diagnostic solutions for memories and other IP blocks in SoCs. The results of their work have been referenced by researchers more than 3,000 times and are widely used as a basis for further investigations in the area.
The integrated testing, recovering and diagnosing solutions for SoCs are used both during manufacturing and in system. These solutions are not only the basis for further research—but they have significant practical value.
They are used in two product lines developed by Synopsys and utilized in more than 300 companies. These products are DesignWare® STAR Memory System® (SMS) IP released in 2001 and DesignWare® STAR Hierarchical System® (SHS) IP released in 2013. Moreover, one of these products, SMS, was honored with the Best in Test Product of the Year award in 2002, and Test & Measurement World Best in Test Award in 2013.
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Posted by Navraj Nandra on January 28th, 2014
PCI Express (PCIe) has long been a dominant standard for communications inside of computers, servers and blades but sometimes you need to think (and send data) outside the box. Since the first release of PCIe cabling standard in early 2007, creative engineers have been looking to utilize this new capability as a box-to-box interconnect, in order to expand PCIe into high end networking applications.
Through the three versions of the PCIe specification two reference clock (Refclk) receiver (Rx) architectures were defined, the common Refclk Rx architecture (Figure. 1a) and the data clocked Rx architecture (Figure. 1b). The difference in the two architectures is the following: In the common Refclk Rx architecture the receiver uses the same reference clock in its Clock and Data Recovery (CDR) as the transmitter and thus the CDR is synchronous with the incoming data. In a data clocked Rx architecture the CDR uses only the edges of the incoming data in its CDR and the Rx CDR needs to track all the jitter on the incoming signal. However, these architectures pertain only to the receiver and in either Rx architecture it is expected that the associated transmitter is synchronous with a system reference clock.
Figure 1a (left) Figure 1b (right)
What this means is that the same reference clock (usually with Spread Spectrum Clocking, a.k.a. SSC) needs to be delivered to both ends of the link. For in-box applications this is not overly burdensome since the PCIe edge connector already has pins to carry this reference clock. However, if it is desired to send PCIe data outside of a box using a cable, the requirement that the reference clock needs to be sent in addition to the data signals is troublesome. While sending the Refclk does not sound like much of a burden it creates two issues: First, the cables and connectors need to be thicker, heavier and more expensive to carry the extra clock signals. Second, even though the Refclk does have SSC on it there can still be a large amount of Electromagnetic Interference (EMI) resulting from sending the Refclk.
How does this EMI arise? If the Refclk were perfectly differential and if the pair of conductors carrying the differential clock were perfectly matched then there would be no return current and little EMI. However, any non-differential element in the clock (either from the clock going into the cable or from mismatch in the conductors carrying the clock signals) causes some Common Mode (CM) signal to develop and the return path for that CM current is through ground. The shield of the cable is ground and thus shield would be a ”good” antenna for the CM signal. This is more problematic for clock signals than data signals because even a clock with SSC on it is relatively narrowband compared to the width of the data spectrum and thus is a stronger aggressor.
What is the solution? Well like the saying goes, I told my doctor it hurts when I do this and he said don’t do that. Thus SRIS (Separate Refclks Independent Spread) was developed to define a usage model with separate reference clocks at each end of a link (Figure 2). Thus, the root complex Refclk does not need to be sent across the cable in a PCIe SRIS application. Also, we note that the Refclk at each end of the link is independently spread to help reduce EMI. This is similar to other standards supporting data exchange of cables such as SATA and USB.
Is there any penalty for not sending the Refclk? The only disadvantage is that now the CDR in the Rx must track the full range of the incoming SSC. However, SATA and USB data clocked architecture receivers already have this situation. Thus, the challenges placed on a receiver in this environment are well understood and manageable by anyone offering any of the aforementioned products.
Thus, SRIS for PCIe is a new usage models to allow PCIe links to exist outside the box, especially for high data rate PCIe 3.0 (8Gbps) and the upcoming PCIe 4.0 (16Gbps) that are planned for quite a few new chassis to chassis interconnect for the high-end networking systems.
Today we announced the availability of the DesignWare Enterprise 12G PHY IP, which includes support for SRIS. You can learn more about SRIS in our new video, Using SRIS in PCIe Systems.
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Posted by Navraj Nandra on December 23rd, 2013
Synopsys’ DesignWare® STAR Hierarchical System has been selected by EDN as a Best in Test 2014 Award Finalist. Every year, the Best-in-Test Awards recognize the best in test products and test professionals. STAR Hierarchical System (SHS) has been nominated for “Best in Test Award” in two categories: “Best in Test 2014 – Semiconductor Test” and “Best in Test 2014 – Product of the Year”. Public voting decides the final winners, which will be announced at DesignCon 2014. This award is a great honor for a test product and you can help DesignWare STAR Hierarchical System win.
The DesignWare STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. The STAR Hierarchical System addresses increasing productivity and low-cost test requirements as SoC test becomes more complex as a result of larger designs and more extensive use of IP. The STAR Hierarchical System:
DesignWare STAR Hierarchical System improves test QoR and accelerate silicon testing of the entire SoC to meet cost, quality and schedule goals
- Automatically creates a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, reducing test integration time and providing easy integration of the SoC test resources
- Gives designers the flexibility to schedule individual IP/cores for parallel or serial testing to optimize test time and power consumption during test, which reduces test cost and increases test quality
- Simplifies SoC test pattern creation and silicon debug using the IEEE 1500 network to port IP- or core-level patterns to the SoC level, and enabling the IP debug test modes from the SoC level
- Helps improve SoC yield by enabling eFUSE programming for calibration and trimming of analog/mixed-signal IP
- Offers design-for-test (DFT) implementation and hierarchical IP and core-level test that lets engineering teams cut their test integration time and bring their designs to market faster, with lower design and test cost
Posted in DDR, Embedded Memory, General - mixed-signal IP, HDMI, PCI Express, SATA, Test, USB | Comments Off
Posted by Navraj Nandra on September 9th, 2013
Targetted for the next generation of digital televisions – known as “Ultra HDTV’s”; HDMI 2.0 has finally arrived after being in works for about 2 years by the broad group of companies in HDMI forum.
The arrival of HDMI 2.0 is very timely for the wide rollout of this new generation of Ultra HDTVs. Since its debut in 2002, every major revision of HDMI specification had a key driving theme, for example, HDMI 1.3 offered higher bandwidth for deep color modes, HDMI 1.4 offered 3D modes etc. The main theme behind HDMI 2.0 is 18 Gbps bandwidth to support 4K resolution at 60Hz frame rate for the ultra-high definition experience. With backwards compatibility as the basic underlying requirement, HDMI 2.0 will offer a broad array of new and exciting features. Here is the summary of new features offered by HDMI 2.0.
- 4K x 2K Mode @ 60Hz, 24-bit color, for the ultra-high definition experience
- Increase in bandwidth from 10.2 Gbps to 18 Gbps aggregate (3.4 Gbps to 6 Gbps per lane) to support the ultra-high definition video formats
- Support for TMDS scrambling above 10.2Gbps data rate to reduce Electro Magnetic Interference (EMI)
- New colorimetry formats such as YCbCr 4:2:0 to offer a visual loss-less ultra-high definition experience with half the required bandwidth
- New 21:9 frame formats for true cinema experience
- Low level error detection to account for cable characteristics
- Multi-stream audio and video for new gaming and infotainment applications
- Up to 32 channels of audio for high end home theatre systems
- High-Efficiency Advanced Audio Coding (HE-AAC) to support lossy data compression scheme for digital audio (MPEG-4 audio profile)
- Consumer Electronic Control (CEC) 2.0 that offers unified remote control for ease of use and improved user experience
As the interface of choice for multimedia devices, the HDMI standard will continue to evolve, offering new features, functionality and higher bandwidth to meet the needs of future applications. The advent of HDMI forum has fostered innovation and lead to broader industry participation. HDMI 2.0 is the first revision that has been architected by this broad group of companies in the forum and offers a plethora of innovative features with potential to revolutionize the home theatre systems by offering cinema quality experience in the comfort of your home. Yet there are other features offered by HDMI 2.0 that will lead to broader adoption of HDMI in industrial, office and gaming applications. We shall soon see the first impact of HDMI 2.0 as the 4K DTV will begin to hit the shelves in next couple of months. Eventually a lot of these features offered by HDMI 2.0 will become “check boxes” while the forum will continue to work on new innovative features and the process of evolution will continue.
HDMI 2.0 Demo And Industry's First 4k Eyes
Synopsys had been a part of HDMI forum since its very inception and had played an active role towards defining the next generation HDMI by bringing the perspective of our broad range of IP customers. Our active participation in the forum also allowed us to develop our HDMI 2.0 solutions, while the specification was being baked. Hours after the announcement of HDMI 2.0, we were able to demo our version 2.0 compliant TX/RX solutions to lead customers in APAC. In fact, we had announced “Industry’s 1st 4K Eyes” in December 2012 to select forum members that we had been working with for next generation DTV SoCs.
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Posted by Navraj Nandra on April 17th, 2013
A wide range of wireless SoCs supporting near field communication (NFC), Bluetooth, 802.11, and other radio applications can reduce both system power and cost by integrating multiple time programmable (MTP) non-volatile memory (NVM) on-chip. The MTP NVM can be used for field updatable lookup tables (for routing NFC packets), device matching (in the case of Bluetooth), customer settings (i.e., volume or radio pre-sets), or general configuration and calibration data.
While embedded MTP has been easily scalable from 350-nm to 65-nm, developing embedded MTP NVM in a standard CMOS process is becoming more difficult as the technology moves to more advanced nodes.
Embedded MTP is typically developed on the concept of storing charge on a floating gate. As the I/O voltage and corresponding gate oxide thickness reduces in advanced process nodes, the intrinsic ability of the process to store charge approaches the theoretical limit. Based on the work of Ielmini et. al1, in order to achieve 10-year data retention, the gate oxide needs to be above 44 angstrom, which falls between the typical gate oxide thickness for a 1.8V and a 2.5V transistor. Traditional embedded flash or embedded EEPROM technology normally requires additional processing which not only adds cost to the manufacturing process but may impact the device performance and may require design modifications to maintain the wireless or RF performance of the SoC. Synopsys’ DesignWare NVM IP addresses both the cost and design drawbacks by developing the IP in standard CMOS processes with no additional masks or processing steps. DesignWare IP has the added advantage of operating solely from the 1.1V supply, with all the necessary high voltage and support circuitry integrated in the NVM block itself.
Synopsys developed MTP in standard CMOS processes starting at 350-nm and now has silicon-proven embedded MTP in an industry leading 40-nm low power process. One of the key challenges in developing MTP in advanced process technologies is managing the stress put on the gate oxide during program and erase operations. At 40-nm, the most common I/O voltage has been reduced to 2.5V, and the gate oxide for these transistors is in the range of 50A. Reliably programming and erasing thousands of times requires a great deal of care and expertise. As I’ve mentioned before, Synopsys has the most thorough and comprehensive characterization and qualification methodology of any embedded NVM IP supplier. Already licensed to multiple customers targeting consumer and industrial wireless applications, Synopsys’ 40-nm embedded MTP is in the process of completing qualification testing and will be generally available within the next few months.
Posted in An analog designer speaks!, Data Converters, Low Power - Analog Designer's Guide | Comments Off
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