HOME    COMMUNITY    BLOGS & FORUMS    The Eyes Have It
The Eyes Have It
  • About

    This blog discusses all things related to mixed-signal PHY IP such as the latest trends, design challenges and anything that may be controversial.

    I built my first crystal radio at about the age of ten (had help with the soldering iron) and have been dabbling in the analog electronics field ever since. The "James Brown of Analog": I do like James Brown and have I been working in the electronics industry for many years. I’m also a big fan of Reggae and Ska and spent my youth listening to John Peel on Radio 1. Ken Boothe is the greatest singer. Running is a passion. Squaw Valley is the best place to ski. Ever!

    - Navraj Nandra

Linking PCI Express Outside The Box

Posted by Navraj Nandra on January 28th, 2014

PCI Express (PCIe) has long been a dominant standard for communications inside of computers, servers and blades but sometimes you need to think (and send data) outside the box. Since the first release of PCIe cabling standard in early 2007, creative engineers have been looking to utilize this new capability as a box-to-box interconnect, in order to expand PCIe into high end networking applications.

Through the three versions of the PCIe specification two reference clock (Refclk) receiver (Rx) architectures were defined, the common Refclk Rx architecture (Figure. 1a) and the data clocked Rx architecture (Figure. 1b). The difference in the two architectures is the following: In the common Refclk Rx architecture the receiver uses the same reference clock in its Clock and Data Recovery (CDR) as the transmitter and thus the CDR is synchronous with the incoming data. In a data clocked Rx architecture the CDR uses only the edges of the incoming data in its CDR and the Rx CDR needs to track all the jitter on the incoming signal. However, these architectures pertain only to the receiver and in either Rx architecture it is expected that the associated transmitter is synchronous with a system reference clock.

Figure 1a (left) Figure 1b (right)

What this means is that the same reference clock (usually with Spread Spectrum Clocking, a.k.a. SSC) needs to be delivered to both ends of the link. For in-box applications this is not overly burdensome since the PCIe edge connector already has pins to carry this reference clock. However, if it is desired to send PCIe data outside of a box using a cable, the requirement that the reference clock needs to be sent in addition to the data signals is troublesome. While sending the Refclk does not sound like much of a burden it creates two issues: First, the cables and connectors need to be thicker, heavier and more expensive to carry the extra clock signals. Second, even though the Refclk does have SSC on it there can still be a large amount of Electromagnetic Interference (EMI) resulting from sending the Refclk.

How does this EMI arise? If the Refclk were perfectly differential and if the pair of conductors carrying the differential clock were perfectly matched then there would be no return current and little EMI. However, any non-differential element in the clock (either from the clock going into the cable or from mismatch in the conductors carrying the clock signals) causes some Common Mode (CM) signal to develop and the return path for that CM current is through ground. The shield of the cable is ground and thus shield would be a ”good” antenna for the CM signal. This is more problematic for clock signals than data signals because even a clock with SSC on it is relatively narrowband compared to the width of the data spectrum and thus is a stronger aggressor.

What is the solution? Well like the saying goes, I told my doctor it hurts when I do this and he said don’t do that. Thus SRIS (Separate Refclks Independent Spread) was developed to define a usage model with separate reference clocks at each end of a link (Figure 2). Thus, the root complex Refclk does not need to be sent across the cable in a PCIe SRIS application. Also, we note that the Refclk at each end of the link is independently spread to help reduce EMI. This is similar to other standards supporting data exchange of cables such as SATA and USB.

Figure 2

 

Is there any penalty for not sending the Refclk? The only disadvantage is that now the CDR in the Rx must track the full range of the incoming SSC. However, SATA and USB data clocked architecture receivers already have this situation. Thus, the challenges placed on a receiver in this environment are well understood and manageable by anyone offering any of the aforementioned products.

Thus, SRIS for PCIe is a new usage models to allow PCIe links to exist outside the box, especially for high data rate PCIe 3.0 (8Gbps) and the upcoming PCIe 4.0 (16Gbps) that are planned for quite a few new chassis to chassis interconnect for the high-end networking systems.

Today we announced the availability of the DesignWare Enterprise 12G PHY IP, which includes support for SRIS. You can learn more about SRIS in our new video, Using SRIS in PCIe Systems.

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in PCI Express | Comments Off

Hierarchical system and IP test – vote for the true STAR!

Posted by Navraj Nandra on December 23rd, 2013

Synopsys’ DesignWare® STAR Hierarchical System has been selected by EDN as a Best in Test 2014 Award Finalist. Every year, the Best-in-Test Awards recognize the best in test products and test professionals. STAR Hierarchical System (SHS) has been nominated for “Best in Test Award” in two categories: “Best in Test 2014 – Semiconductor Test” and “Best in Test 2014 – Product of the Year”. Public voting decides the final winners, which will be announced at DesignCon 2014. This award is a great honor for a test product and you can help DesignWare STAR Hierarchical System win.

The DesignWare STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. The STAR Hierarchical System addresses increasing productivity and low-cost test requirements as SoC test becomes more complex as a result of larger designs and more extensive use of IP. The STAR Hierarchical System:

DesignWare STAR Hierarchical System improves test QoR and accelerate silicon testing of the entire SoC to meet cost, quality and schedule goals

  • Automatically creates a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, reducing test integration time and providing easy integration of the SoC test resources
  • Gives designers the flexibility to schedule individual IP/cores for parallel or serial testing to optimize test time and power consumption during test, which reduces test cost and increases test quality
  • Simplifies SoC test pattern creation and silicon debug using the IEEE 1500 network to port IP- or core-level patterns to the SoC level, and enabling the IP debug test modes from the SoC level
  • Helps improve SoC yield by enabling eFUSE programming for calibration and trimming of analog/mixed-signal IP
  • Offers design-for-test (DFT) implementation and hierarchical IP and core-level test that lets engineering teams cut their test integration time and bring their designs to market faster, with lower design and test cost

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in DDR, Embedded Memory, General - mixed-signal IP, HDMI, PCI Express, SATA, Test, USB | Comments Off

HDMI 2.0 For The Future High Definition Televisions

Posted by Navraj Nandra on September 9th, 2013

Targetted for the next generation of digital televisions – known as “Ultra HDTV’s”; HDMI 2.0 has finally arrived after being in works for about 2 years by the broad group of companies in HDMI forum.

The arrival of HDMI 2.0 is very timely for the wide rollout of this new generation of Ultra HDTVs. Since its debut in 2002, every major revision of HDMI specification had a key driving theme, for example, HDMI 1.3 offered higher bandwidth for deep color modes, HDMI 1.4 offered 3D modes etc. The main theme behind HDMI 2.0 is 18 Gbps bandwidth to support 4K resolution at 60Hz frame rate for the ultra-high definition experience. With backwards compatibility as the basic underlying requirement, HDMI 2.0 will offer a broad array of new and exciting features. Here is the summary of new features offered by HDMI 2.0.

  • 4K x 2K Mode @ 60Hz, 24-bit color, for the ultra-high definition experience
  • Increase in bandwidth from 10.2 Gbps to 18 Gbps aggregate (3.4 Gbps to 6 Gbps per lane) to support the ultra-high definition video formats
  • Support for TMDS scrambling above 10.2Gbps data rate to reduce Electro Magnetic Interference (EMI)
  • New colorimetry formats such as YCbCr 4:2:0 to offer a visual loss-less ultra-high definition experience with half the required bandwidth
  • New 21:9 frame formats for true cinema experience
  • Low level error detection to account for cable characteristics
  • Multi-stream audio and video for new gaming and infotainment applications
  • Up to 32 channels of audio for high end home theatre systems
  • High-Efficiency Advanced Audio Coding (HE-AAC) to support lossy data compression scheme for digital audio (MPEG-4 audio profile)
  • Consumer Electronic Control (CEC) 2.0 that offers unified remote control for ease of use and improved user experience

As the interface of choice for multimedia devices, the HDMI standard will continue to evolve, offering new features, functionality and higher bandwidth to meet the needs of future applications. The advent of HDMI forum has fostered innovation and lead to broader industry participation. HDMI 2.0 is the first revision that has been architected by this broad group of companies in the forum and offers a plethora of innovative features with potential to revolutionize the home theatre systems by offering cinema quality experience in the comfort of your home. Yet there are other features offered by HDMI 2.0 that will lead to broader adoption of HDMI in industrial, office and gaming applications. We shall soon see the first impact of HDMI 2.0 as the 4K DTV will begin to hit the shelves in next couple of months. Eventually a lot of these features offered by HDMI 2.0 will become “check boxes” while the forum will continue to work on new innovative features and the process of evolution will continue.

HDMI 2.0 Demo And Industry's First 4k Eyes

Synopsys had been a part of HDMI forum since its very inception and had played an active role towards defining the next generation HDMI by bringing the perspective of our broad range of IP customers. Our active participation in the forum also allowed us to develop our HDMI 2.0 solutions, while the specification was being baked. Hours after the announcement of HDMI 2.0, we were able to demo our version 2.0 compliant TX/RX solutions to lead customers in APAC. In fact, we had announced “Industry’s 1st 4K Eyes” in December 2012 to select forum members that we had been working with for next generation DTV SoCs.

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in HDMI | Comments Off

Multi-programmable non-volatile memory on standard 40-nm CMOS

Posted by Navraj Nandra on April 17th, 2013

A wide range of wireless SoCs supporting near field communication (NFC), Bluetooth, 802.11, and other radio applications can reduce both system power and cost by integrating multiple time programmable (MTP) non-volatile memory (NVM) on-chip. The MTP NVM can be used for field updatable lookup tables (for routing NFC packets), device matching (in the case of Bluetooth), customer settings (i.e., volume or radio pre-sets), or general configuration and calibration data.

While embedded MTP has been easily scalable from 350-nm to 65-nm, developing embedded MTP NVM in a standard CMOS process is becoming more difficult as the technology moves to more advanced nodes.

Embedded MTP is typically developed on the concept of storing charge on a floating gate. As the I/O voltage and corresponding gate oxide thickness reduces in advanced process nodes, the intrinsic ability of the process to store charge approaches the theoretical limit. Based on the work of Ielmini et. al1, in order to achieve 10-year data retention, the gate oxide needs to be above 44 angstrom, which falls between the typical gate oxide thickness for a 1.8V and a 2.5V transistor. Traditional embedded flash or embedded EEPROM technology normally requires additional processing which not only adds cost to the manufacturing process but may impact the device performance and may require design modifications to maintain the wireless or RF performance of the SoC. Synopsys’ DesignWare NVM IP addresses both the cost and design drawbacks by developing the IP in standard CMOS processes with no additional masks or processing steps. DesignWare IP has the added advantage of operating solely from the 1.1V supply, with all the necessary high voltage and support circuitry integrated in the NVM block itself.

Synopsys developed MTP in standard CMOS processes starting at 350-nm and now has silicon-proven embedded MTP in an industry leading 40-nm low power process. One of the key challenges in developing MTP in advanced process technologies is managing the stress put on the gate oxide during program and erase operations. At 40-nm, the most common I/O voltage has been reduced to 2.5V, and the gate oxide for these transistors is in the range of 50A. Reliably programming and erasing thousands of times requires a great deal of care and expertise. As I’ve mentioned before, Synopsys has the most thorough and comprehensive characterization and qualification methodology of any embedded NVM IP supplier. Already licensed to multiple customers targeting consumer and industrial wireless applications, Synopsys’ 40-nm embedded MTP is in the process of completing qualification testing and will be generally available within the next few months.

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in An analog designer speaks!, Data Converters, Low Power - Analog Designer's Guide | Comments Off

Ethernet Summit – Getting 10Gb/s On Your Chip

Posted by Navraj Nandra on March 29th, 2013

The Ethernet Technology Summit, April 2nd to 4th at the Santa Clara Marriot in San Jose, focuses on the use of Ethernet throughout the networking space. This includes the emergence of 10-Gigabit Ethernet as a key LAN technology on the desktop and in data centers. I will be addressing the requirements of including 10G IP on a networking chip.

The summit also covers the emerging standards for 40-Gigabit and 100-Gigabit Ethernet. It also includes the use of Ethernet as a carrier backbone and transport method, as well as in storage applications and in virtualized data centers and clouds. Other topics of interest include design and development, fabrics, chipsets and components, security, delay and packet loss, convergence, big data, and market research. .

As the most common LAN technology, Ethernet is widely used and understood. Standards are managed through IEEE (IEEE 802), and work on new standards proceeds continously. Chips, parts, boards (particularly network interface cards or NICs), and expertise are all widely available. The Ethernet ecosystem is large and has many significant players, such as Cisco Systems, Intel, Broadcom, Marvell, Alcatel-Lucent, Hewlett-Packard, and Ericsson. Trade groups such as the Ethernet Alliance and MEF are very active and promote education, testing, and certification.

Challenges facing ethernet: Need for higher speed with 100-Gigabit Ethernet on the horizon, need for management, quality assurance, and security tools as Ethernet moves into service provider networks, reducing power usage, increasing bandwidth, and the need for software to handle storage-over-Ethernet and new approaches such as convergence and Fibre Channel over Ethernet.

Major Issues covered during the conference include: Higher speed, higher effective bandwidth, lower power consumption, quality-of-service, security, management tools, test equipment, certification and convergence.

Key notes include: “Welcome to the Generation of Open Ethernet” by Eyal Waldman CEO Mellanox, “Ethernet’s Next Step: 400 Gigabit” by John D’Ambrosia, Chairman Ethernet Alliance, “The Next 40 Years of Ethernet” by Jane Li COO Huawei Enterprise US, “Unified Data Center for the Cloud Era” by David Yen, Senior VP/GM Cisco.

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in General - mixed-signal IP | Comments Off

Embedded Vision Through Other Eyes

Posted by Navraj Nandra on March 26th, 2013

Embedded Vision is a hot application these days. For those of you who have kids, you may have experienced already a lot of it from the gesture recognition area with the Kinect box. Samsung’s Galaxy S4 sports a camera that detects your finger pointing in the air to steer the user interface. And sooner than you expect your car will automatically break if you don’t notice the pedestrian crossing the street. What do all of these applications have in common? All of them have a camera sensor that is followed by sophisticated, real-time image processing that extracts the information that is relevant for the application.

In many cases for example (the pedestrian is a good case for that) it is sufficient to detect the edges of an object in the first place. I had the chance to experience my own edges recently as I walked up to an embedded vision processor demonstration on the 2013 SNUG Design Community Expo show floor this week. My body contour showed up as a spider web of white lines on the monitor in real-time as I was moving in front of the camera screen. What I actually saw was a specialized processor designed with a nifty tool, Synopsys Processor Designer. The embedded vision processor had been implemented on a HAPS(r) prototyping system that also had the daughter card with the HDMI outputs driving the screen and the AVI input from the camera. I was told that my image could be slightly improved by fine tuning the algorithm parameters, but from an edge detection perspective I was looking just fine….

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in Uncategorized | Comments Off

Free beer, a race track, FinFET’s, an IP summit, and memory test

Posted by Navraj Nandra on March 20th, 2013

Ok. So now I’ve got your attention :-) SNUG is where you will find all these and more!

Next Monday, Tuesday and Wednesday is our annual SNUG (Synopsys Users’ Group) at the Santa Clara Convention Center. Registration closes tomorrow noon-time (Thursday March 21st at 12PM – see registration link at the end of the post).

Monday will feature the IP Summit, comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries presented by Verisilicon and Imagination; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. Both days will provide ample opportunity to learn formally through tutorials, panels and presentations from customers and our R&D team on FinFET technology; and, informally through networking opportunities.

On Wednesday morning, my good friend and colleague, Dr. Yervant Zorian will deliver a tutorial on “Embedded Memory Test, Repair & Diagnostics”. He will address the very interesting topic facing SoC developers today, that yield relies heavily on memory yield. There is greater manufacturing complexity in 20-nm and FinFET technology nodes, which create new yield challenges, both in the form of increased defect densities and in the form of new types of failure mechanisms that need to be modeled for accurate detection, diagnosis, and repair. So, it is essential to have an embedded memory test and repair solution that not only meets the above challenges for today’s designs, especially those at 20-nm and below, but that is also cost-effective. Yervant will include a description of a new hierarchical embedded memory test and repair architecture, resulting in a 30% area reduction compared to the previous generation, support for high performance processor cores and advanced test, repair and diagnostics algorithms that target designs on advanced planar and FinFET technology nodes.

Oh, yes the beer and race track. Here are the details:

Where: SNUG Pub – The largest pub in silicon valley
When: Tuesday, March 26, 4:45 – 7:00 PM
What: SNUG Pub Grand Prix, you will be able to see our involvement in the automotive industry and will be able to test your driving skills and compete at the “SNUG Pub Grand Prix” at the Micro -Reality Race Track or the Daytona II Racing Simulators from 4:45 to 7:00 pm. It will be a great way to relax and have fun!

And…Yervant and I like beer and we love discussing what we do, so looking forward to seeing you next week.

SNUG registration closes tomorrow noon. Please visit www.synopsys.com and follow the links.

SNUG Pub - The largest pub is silicon valley - I know I've been to most of them!

SNUG Pub Racetrack

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in An analog designer speaks!, DDR, Embedded Memory, General - mixed-signal IP, Logic Libraries, Low Power, Low Power - Analog Designer's Guide | Comments Off

Shifting up MIPI M-PHY to gear 3 – a silicon demo

Posted by Navraj Nandra on March 18th, 2013

The MIPI M-PHY was developed for mobile devices where the important requirements were low pin count combined with very good power efficiency and high electro-migration interference (EMI) immunity. High performance is achieved through “gears”.

Gear 1 at 1.45 Gbps per lane, Gear 2 at 2.9 Gbps per lane and Gear 3 at 5.8 Gbps/lane. Mobile devices can be sensitive to EMI, and each gear of the M-PHY has two frequencies that are close together allowing to select the optimum from an radio receiver sensitivity perspective. Depending on your bandwidth needs you can go up to eight lanes. The picture below shows the M-PHY, it supports a number of protocols for different applications such as camera serial interfaces to camera sensors, internal displays, USB 3.0 or PCI Express protocols for chip to chip interfacing. For embedded storage, the next generation after the embedded multi-media card (eMMC) will be universal flash storage (UFS), a protocol the overlays the M-PHY.

MIPI M-PHY supporting many protocols for popular mobile requirements

So the point is that there are many applications and protocols that will use the MIPI M-PHY and the bandwidth needs are increasing. The latest specification to support the emerging bandwidth needs is Gear 3. This week during the MIPI Alliance face-to-face meeting in Asia, we will be demonstrating the first silicon proven M-PHY operating at High Speed Gear3.

Posted in Low Power, PCI Express, Uncategorized | Comments Off

An IP Summit In The Heart Of Silicon Valley

Posted by Navraj Nandra on March 12th, 2013

We will be hosting our annual Synopsys user’s group meeting (SNUG) in Santa Clara this month. We will feature an IP Summit comprising seven design tutorials on: CPU hardening using our memories and standard cell logic libraries; a lunch and learn on FinFET technology; a tutorial on analog/mixed-signal design using FinFET devices; DDR solution integration; 10G backplane design; DDR4 timing budgets; PCI Express in the Cloud; Improving SoC performance through memory optimization. You can register on
http://www.synopsys.com/IP/Pages/ipsummit2013.aspx
These tutorials provide insights into today’s IP development challenges and what may impact your design thinking in the future, propose solutions; presented by industry experts and this event will also provide a unique networking opportunity with IP developers, SOC design architects and system engineers.

I’m in the process of completing a tutorial “20-nm Mixed-Signal IP – A Stepping Stone to 16-nm FinFET?” (presented on Monday March 25th) I’m coming to the following conclusions, would be great to get your opinions too! Looking forward to seeing you.

1. Power, performance and area drives IP specifications for the analog/mixed-signal designer, these are achieved through architectural or schematic level design changes in advanced planar and FinFET designs

2. Analog process qualification vehicles are necessary to provide insight into the impact of the early design rules and process parameters on performance

3. FEOL impacts FinFET processes; key learning (stepping stone) from planar is DPT and device quantization

4. FinFET impacts analog parameters; completely new layout structures needed

5. Engineers will leverage FinFET physical properties and invent new circuits

You can register on http://www.synopsys.com/IP/Pages/ipsummit2013.aspx

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in DDR, Embedded Memory, General - mixed-signal IP, Logic Libraries, PCI Express | Comments Off

Is 20-nm planar a stepping stone to FinFET’s; can analog IP be re-used?

Posted by Navraj Nandra on February 26th, 2013

Word has it that 14-nm or 16-nm fInFET processes are based on a planar CMOS 20-nm “back-end-of-line”. We’ll get into what back-end-of-line means in a later blog post. For now consider what the first statement implies since it is touted in the industry as a “fast and low risk ramp to finFET’s”, that the expertise developed for a 20-nm analog/mixed-signal IP design could be leveraged. But is this really be true? And is this the right question? IP reuse is about time to market, however, what an analog/mixed-signal designer really cares about is to get performance by the realization of higher fT and fmax, achieved by higher transconductance, output resistance, low gate capacitance and resistance. Nothing new here – this is our daily job as analog designers. The consumer of the IP, in many cases the SoC architect not only cares about time to market but also power, performance and area. Plus the IP must work on the first instantiation. The last two points are opening up new design possibilities for the analog designer. Going back thirty years, the initial CMOS circuits were based on the bipolar equivalents but over time new techniques such switched capacitor circuits started to appear as analog designers started to exploit the property of MOSFETS. We are at the same juncture with finFET’s.

The interconnects and dual pattern technology are similar to planar technologies but the devices are very different. In March, I will talking in more detail on this topic at SNUG San Jose. Going into how 20-nm planar designs require a much deeper link between layout and power, performance and area requirements compared to previous nodes. Furthermore, quantization of these devices means that the 20-nm planar development is from the ground up, so you can’t reuse even at the 28-nm node. I’ll be providing design examples and will let you determine whether 20-nm is truly a stepping stone to finFET’s.

Regardless, this is an exciting time to be analog/mixed-signal designer!

Share and Enjoy:
  • del.icio.us
  • Digg
  • Facebook
  • Google Bookmarks
  • Print
  • Twitter
  • StumbleUpon
  • LinkedIn
  • RSS

Posted in An analog designer speaks!, Uncategorized | Comments Off