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This is going to be a pretty boring post, without much drama. But, I think that’s OK (once in a while). Let me explain.

In the world of national and international politics, sensational news of conflict often gets more media attention than stories of cooperation, collaboration and progress.   Much the same happens in the world of electronic design automation, albeit at a much smaller scale.  Editors and bloggers alike are drawn to controversy, like moths to a light, in an effort to get more readers or pump up circulation.  Verilog vs VHDL!  Vera vs. Specman! SystemVerilog vs. SystemC!  VMM vs OVM! Some readers are also drawn to this for the vicarious thrill of seeing their favorite company or technology face off against an opponent.  It’s hard not to get caught up in it! Sometimes these debates actually help drive progress and consensus, but very often they are based on a false argument and end up annoying chip developers who just want to get their design out.

Stories of cooperation and interoperability tend to get less airtime amongst the media, perhaps because it is expected that companies will just make things work.  In the developed world, nobody writes stories about how the lights turn on or the phone works or the water runs.  However, I’d say that the EDA industry is not quite as developed as the public infrastructure in advanced countries.  Complex chip development technologies created by independent, competing companies don’t “just work” together without consistent focused effort and significant involvement from end users.

This Thursday (November 5) in Santa Clara, Synopsys will be celebrating the progress made over the past year in EDA interoperability and standards at its 22^nd EDA Interoperability Forum with the theme “Peace, Love and Interoperability”.  This all-day event, held at the Sun Conference Center at Agnes Historic Park, is open for both EDA tool developers and IP/chip developers.

The agenda includes quite a bit for verification-minded folks: learn the latest developments around SystemC TLM 2.0 for interoperable system-level models, the latest VMM methodology updates for interoperable verification environments, and the HapsTrak interface for open connectivity to FPGA-based rapid prototypes.  As an added bonus, the first 100 attendees will receive free copies of the VMM for Low Power book, and Doulos’ VMM Golden Reference Guide.

Registration is free, and breakfast and lunch is provided. I hope to see you there!

Do you have an elevator pitch for your IP, chip or system? Don’t say “I’m an engineer – pitching is marketing’s job!” Everyone developing technology products should be able to deliver their product’s elevator pitch.

Engineers have a strong tendency to quickly dive down into the technical minutiae of their product and lose the big picture. However, this detail often overwhelms and obscures the importance of their great new technology. Whether you develop IP, chips, electronic systems or even EDA software, the ability to effectively communicate the value and relevance of your product (or the feature you are working on) will help you stay connected to what is important for the product, your company and the customer.

An elevator pitch shouldn’t be long – less than a minute. It is a concise explanation of your product that you could give to your CEO (or your customer’s CEO or a potential investor’s CEO) should you find yourself next to him or her on an elevator for a few floors.

I’ll admit that in my 20 years in the semiconductor industry I haven’t often found myself in a position to give a pitch to a CEO who happened to be standing next to me in an elevator (lots of single-story buildings in Silicon Valley, I guess). But the process of crafting an elevator pitch is valuable in itself. It is a process to help crystallize in your mind the value proposition, target user and competitive differentiation of your product or feature – all very good things for engineers and marketeers alike to know.

Here’s my favorite way to quickly put together an elevator pitch, from the technology marketing classic Crossing the Chasm (I must be a real fan of Geoffrey Moore!). Just fill in the blanks and you’ll have a concise, compelling elevator pitch for your product or feature:

• For (target customers)
• Who (statement of the need or opportunity)
• The (product name) is a (product category)
• That (statement of key benefit – that is, compelling reason to buy)
• Unlike (primary competitive alternative)
• Our product (statement of primary differentiation)

Let’s try a few examples. Suppose we are Amdahl, a maker of plug-compatible clones of IBM mainframe, and let us say that our primary competitive alternative is Hitachi Data Systems. Our elevator message might be:

For Fortune 500 companies who are looking to cut costs and who operate in data centers of IBM mainframe computers, Amdahl’s computers are plug-compatible mainframes that match or surpass the equivalent IBM computers in features and performance, at a far more attractive price. Unlike the Hitachi line of computers, our products have been backed by the same service and support organization for over 20 years.

Crossing the Chasm, p. 161

Geoffrey Moore

What’s your elevator pitch?

I thought I would break the ice on my first blog post here and tell you a little bit about myself and my history in verification. (well, it was actually not my thought but rather a suggestion from fellow blogger Karen Bartleson over at The Standards Game , that helped me break my writer’s block and get started on this…Thanks Karen!)

I verified my first design way back in 1990 when I was an ASIC designer at Matsushita in Osaka. My chip was a video image processor / system controller for a “TV Door Phone ”, and we were the first team to use this new-fangled VHDL language, logic synthesis and HDL simulation (anyone remember the Very Slow Simulator? . Top-down design was very cool back then, and I was able to run the same simulations (I don’t think we called them testbenches yet) against high level models, RTL and netlists. Analysis was quite a chore; I remember having to tape multiple 3-meter long waveform printouts up on the wall to really understand what was happening throughout a complete video frame. I also recall very long nights as we approached our tapeout date, trying to complete timing verification of our scan chains and wondering if we had missed any errors in the functional waveforms. In the end we taped out not when verification was complete, but when my boss said “time’s up!”. Sound familiar? In the end, the gate array came back and worked, apart from about half of the scan chains with hold-time violations. We finished the entire design, from concept and tool selection to working first-silicon in a year. Top-down design was declared a success!

I then joined the EDA industry with a variety of startups, focusing on DFT, design services, FPGA synthesis, code coverage and functional verification until joining Synopsys five years ago to focus on testbench languages, tools and methodologies.

One of the interesting things I’ve observed over the past few years is how complex verification has become. Million line testbenches? Object-oriented programming? It seems like you have to be a software engineer to do verification anymore. But, without constrained-random testbenches, powerful debug environments and very fast simulators I can’t imagine how anyone could verify a modern chip – certainly not by taping waveforms on the wall and hoping you didn’t miss anything! “Hope ” may be a mantra for the new Obama administration, but I don’t think it’s the best way to verify your design!

And it’s just not about digital simulation anymore. Chips have really become Systems on Chips, with mixed signal blocks, multiple embedded processors, 3^rd party IP, lots of embedded software and globally-distributed design teams becoming the norm for most designs, rather than the exception. How to efficiently verify these super-complex chips and systems from both a technology/methodology perspective and an organizational/economic perspective is what I’m interested in now, and what I look forward to writing about in the coming months.

Until then, keep your eye On Verification!