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On Verification: A Software to Silicon Verification Blog
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    Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!

    I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!

    - Tom Borgstrom

Getting the last 20%

Posted by Tom Borgstrom on July 6th, 2010

I am happy to write that Nusym’s pioneering coverage convergence technology is now part of Synopsys.

Over the years, I’ve seen the “long pole” in verification schedules shift based on the evolution of verification technologies and chip architectures.  A few years ago one of the long poles was writing tests – it was nearly impossible to think of and write the tests required to verify all of the likely operational scenarios for a complex design.  Fortunately constrained-random verification with SystemVerilog emerged and made it much easier to automatically generate the thousands of tests needed.  Today it is not uncommon to go from 0% to 80% coverage in just a few days after the SystemVerilog testbench is up & running.

What about the remaining 20%?

Today, one of the long poles in verification is coverage convergence – the process where verification engineers analyze the coverage generated by constrained-random tests, identify gaps or “coverage holes”, and adjust the verification environment to try to fill the gaps.  If you think this sounds laborious, repetitive and time-consuming you’d be correct.  I’ve spoken to chip designers who say a third of their overall chip development schedule is spent in this iterative, largely manual, coverage convergence phase of verification.

Automating the coverage convergence process is one of the grand challenges in functional verification.  Closing coverage holes requires precise control over logic buried deep in a design using only external design signals.  This is tough enough for verification engineers – hence all the time spent on coverage convergence.  It can be even harder for a tool to automate completely.  VCS currently offers automated coverage convergence for inputs through its Echo technology.  But what about coverage that is deeply buried in a design, many sequential levels deep from the design inputs?

Nusym’s automated coverage convergence technology is targeted at just this challenge.  Nusym arguably invented the concept of automated coverage convergence back in 2004, and received glowing customer testimonials over the years (here, here, and here).  Their technology shows great promise both in providing focused feedback needed to debug coverage issues, as well as in intelligently generating stimulus to target coverage holes anywhere in the design or testbench. I look forward to this technology bringing down the “long pole” of coverage convergence!

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2 Responses to “Getting the last 20%”

  1. Sean Murphy says:

    It’s been said that “the technology is nothing without the team.”

    What’s your perspective?

  2. Tom Borgstrom says:


    The team behind any advanced EDA technology is as important as (and sometimes more important than) the technology itself. That’s why the majority of the Nusym technical team has joined Synopsys.