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On Verification: A Software to Silicon Verification Blog
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    Who knows what the future will bring! After implementing neural networks in analog CMOS for my MSEE at Ohio State, I moved to Japan to do digital ASIC design using the new VHDL language and fancy logic synthesis technology from a startup called Synopsys. This introduced me to the wonderful world of EDA, where I was able to explore lots of other cool new technologies from test automation at CrossCheck to FPGA synthesis at Exemplar to code coverage at TransEDA to testbench automation and methodology at Synopsys. Twenty years flew by in the blink of an eye!

    I am starting a new exploration around the bigger picture of what it takes to verify and validate increasingly complex designs on increasingly compressed schedules and budgets. This broad topic ranges from technology to economics, from embedded software development and architecture analysis to RTL and circuit design; from personal productivity to distributed team efficiency; from novel ideas to fundamental paradigm shifts; from historical perspectives to predictions of future requirements. Please join me and share your thoughts on verification!

    - Tom Borgstrom

Welcome to On Verification!

Posted by Tom Borgstrom on January 21st, 2009

I thought I would break the ice on my first blog post here and tell you a little bit about myself and my history in verification. (well, it was actually not my thought but rather a suggestion from fellow blogger Karen Bartleson over at The Standards Game , that helped me break my writer’s block and get started on this…Thanks Karen!)

I verified my first design way back in 1990 when I was an ASIC designer at Matsushita in Osaka. My chip was a video image processor / system controller for a “TV Door Phone”, and we were the first team to use this new-fangled VHDL language, logic synthesis and HDL simulation (anyone remember the Very Slow Simulator? ;). Top-down design was very cool back then, and I was able to run the same simulations (I don’t think we called them testbenches yet) against high level models, RTL and netlists. Analysis was quite a chore; I remember having to tape multiple 3-meter long waveform printouts up on the wall to really understand what was happening throughout a complete video frame. I also recall very long nights as we approached our tapeout date, trying to complete timing verification of our scan chains and wondering if we had missed any errors in the functional waveforms. In the end we taped out not when verification was complete, but when my boss said “time’s up!”. Sound familiar? In the end, the gate array came back and worked, apart from about half of the scan chains with hold-time violations. We finished the entire design, from concept and tool selection to working first-silicon in a year. Top-down design was declared a success!

I then joined the EDA industry with a variety of startups, focusing on DFT, design services, FPGA synthesis, code coverage and functional verification until joining Synopsys five years ago to focus on testbench languages, tools and methodologies.

One of the interesting things I’ve observed over the past few years is how complex verification has become. Million line testbenches? Object-oriented programming? It seems like you have to be a software engineer to do verification anymore. But, without constrained-random testbenches, powerful debug environments and very fast simulators I can’t imagine how anyone could verify a modern chip – certainly not by taping waveforms on the wall and hoping you didn’t miss anything! “Hope” may be a mantra for the new Obama administration, but I don’t think it’s the best way to verify your design!

And it’s just not about digital simulation anymore. Chips have really become Systems on Chips, with mixed signal blocks, multiple embedded processors, 3rd party IP, lots of embedded software and globally-distributed design teams becoming the norm for most designs, rather than the exception. How to efficiently verify these super-complex chips and systems from both a technology/methodology perspective and an organizational/economic perspective is what I’m interested in now, and what I look forward to writing about in the coming months.

Until then, keep your eye On Verification!

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2 Responses to “Welcome to On Verification!”

  1. harry the ASIC guy says:

    Welcome Fellow Blogger!!!

    I feel like I already know you.

    harry the ASIC guy

  2. tborgstrom says:

    Thanks Harry! Good to join you in the blogosphere!