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Design for Phablets

Posted by Hezi Saar on March 6th, 2013

I spent last week at Mobile World Congress 2013 in Barcelona, where Synopsys also demonstrated our D-PHY, CSI-2 and DSI protocols running in hardware and connecting to Agilent test equipment and UNH conformance test suite.

I also gave a short presentation discussing the challenges designers face when designing SoC’s for use in mobile electronics such as media phones, smartphones, tablets and ultrabooks, or maye as a portmanteau Phablet.
The presentation covered the interfaces commonly found in Phablet SoC’s (I’m starting to like this portmanteau…) and the convergence I believe is driven by the common use cases as well as design and manufacturing costs that have to be amortized across many applications.
In addition to cable connection like USB, HDMI or MHL, the SoC supports a variety of interfaces ‘in-the-box’ such as embedded displays, image sensors, storage, and chip-to-chip connectivity to wireless ICs, Baseband or RFICs.

Synopsys’ efforts in delivering IP for Phablets include providing future proof and silicon proven IP and also working with device vendors to achieve interoperability which is very important for new standard adoption.
A good example of interface convergence is the use of M-PHY and the unique position Synopsys has in delivering silicon proven HS-Gear3 M-PHY for customers who wish to adopt a variety of M-PHY based protocols like JEDEC UFS, MIPI UniPro/CSI-3, USB3.0 SSIC and M-PCIe. This implementation allows most flexibility in achieving lowest total power, supporting latest progression of protocols, and promotes IP re-use.

Stay tuned for more news next week.

[this post was edited on March 12, 2013]


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Posted in Application processor, Baseband processor, Camera, CSI, D-PHY, DigRF, Display, DSI, Image signal processor, LLI, M-PHY, MIPI alliance, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

JEDEC UFS v1.1 in Silicon

Posted by Hezi Saar on February 8th, 2013

Toshiba’s launch of the Industry’s First Embedded NAND Flash memory module compliant with JEDEC UFS v1.1 marks an impressive milestone for the mobile storage market space.

This memory is capable of driving 2.9Gbps compliant with M-PHY Gear2 Rate B and these samples are intended for evaluation by SoC and OS vendors. JEDEC UFS v1.1 is based on MIPI UniPro and MIPI M-PHY and implements functions compatible with eMMC v4.51 but include protocol improvements such as usage of SCSI Command set, Command queueing, Context ID and Data tagging which enable higher performance.

Synopsys is also first in UFS (and UniPro), back in October 2012 we have demonstrated interoperability between our UFS Host solution in Hardware connecting to (yes, you guessed right) Toshiba UFS device hardware implementation. Both solutions are compliant to UFS v1.1. See video here:

Being first to market can’t be a bad thing. The “first mover advantage” is actually a key parameter that determines the business success in the long run. Assuming JEDEC UFS standard becomes popular, the next inflection point in the market where other Storage vendors could catch up is when JEDEC UFS v2.0 is introduced. This is why we are an integral part of the JEDEC UFS work group, MIPI UniPro work group and MIPI PHY workgroup and sub-groups where important decisions about the specification take place.


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Posted in Application processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

First JEDEC UFS v1.1 Host and Device Interoperability

Posted by Hezi Saar on December 13th, 2012

I want to share a video showing the work we are doing at Synopsys to help semiconductor vendors adopt the JEDEC UFS v1.1 standard needed for high performance storage applications. The video shows the Synopsys UFS Host solution connecting with the Toshiba UFS Device prototyping platform and operating a sequence of read and write commands. These commands are sent from the host to the device to store and fetch the data from on-board NVM using the UFS link. As you can expect we have done more comprehensive interoperability tests beyond that.

The interoperability test was done back in October 2012 and it is the first UFS Host and Device interoperability between a ‘host’ company (Synopsys) and a ‘device’ company (Toshiba). What does it mean to be first to demonstrate system level interoperability of this new JEDEC UFS standard?
It means we have a complete and working solution, we can demonstrate it, we can license our proven IP to potential semiconductor vendors who want to adopt UFS v1.1, we can support customer’s hardware prototyping needs and we help reduce the risk of adopting the new UFS standard by conducting these interoperability tests with UFS device vendors.
It means we have a mature solution that can be used today for SoC’s that want to adopt the JEDEC UFS standard.

We (Synopsys) continue to invest in creating a healthy and robust eco-system by driving these mobile electronics standards in JEDEC and MIPI alliance and conducting interoperability tests with device vendors.
Want to learn more about UFS implementation? here’s a nice article that you can read and here’s a joint webinar between MIPI Alliance and JEDEC that will give you a good overview. For those who like to read specifications, here’s a link to a free download the UFS v1.1 spec.


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Posted in Application processor, Image signal processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

DigRFv4 System Demo

Posted by Hezi Saar on November 8th, 2012

Mobile devices that use baseband processors and RFIC’s require a lot of effort to integrate these componenets together in a very challenging environment: small and slim board, tight casing, lots of RF components that may cause noise. Adding to that integrating new interface between the baseband processor and RFIC makes this integration work even more difficult. Synopsys can assist and reduce the integration risk and interface adoption easy for those who selects to integrate this kind of interface, namely the DigRFv4.
Here’s a short video that demonstrates our integration effort with hardware prototyping system that emulates the baseband processor DigRFv4 interface and connects to Fujitsu RFIC hardware system.

This demonstration shows the data flow from baseband to RFIC and back. If you are considering to use DigRFv4 interface in your next design this setup demonstrates proven system-level interoperability that reduces unknowns of the design.


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Posted in Baseband processor, DigRF, LLI, M-PHY, MIPI alliance, RFIC, Smartphone, Tablet | Comments Off

TTS: Time-To-Standard

Posted by Hezi Saar on October 30th, 2012

 

It takes time to bring a standard solution. Starting from a problem, idea, collaboration and specification to a standard use in the market. It takes a very long time to build an eco-system around a new standard and have it proliferated in many designs.
Lets take DigRF spec for example and quickly look at the history. DigRF was established as a MIPI Alliance work group in April 2007. The goal was to develop a specification that will standardize the interface between baseband processors and RFIC’s for existing and future air traffic standards such as 2.5G, 3G, LTE and LTE-Advanced. DigRF 3G was the first specification released that addressed the dual mode 3GPP-compatible 3G /2.5G (UMTS/EGPRS) implementations and later extended to later versions of 3G. In July 2008 the DigRF 3G v3.09.04 specification was approved for release to MIPI members. This specificaiton saw some implementations but was not future-proof for higher bandwidth air links so naturaly that limited the adoption.

DigRFv4 interface was specified to target the continuous increase in air links bandwidth, demand for higher channel bandwidth, IQ sample rates and bit width, RX diversity and MIMO. In addition DigRFv4 aimed at standardizing the link between baseband and RFIC and use a scalable physical layer for that purpose as the work group envisioned the demand for higher bandwidth. DigRv4 is the first protocol that used the MIPI M-PHY due to its scalability, low power and low EMI capabilities.

In May 2010 the DigRFv4 v1.00.00 spec was approved and those vendors who were embedded in the work group and already worked on the implementation started releasing their products to the market. Here’s a link to a public release made at that time: Synopsys claims industry’s first MIPI DigRF v4 IP. And a release of DigRFv4 v1.10 spec followed this year: MIPI® Alliance Advances Radio Frequency Interface Technology in Mobile Devices.

Today we see a selection of baseband processors and RFIC’s that use this DigRFv4 interface, here are a few examples of RFIC and baseband processor solutions:
* Fujitsu RFIC
* Sequans baseband for LTE
* Marvell LTE thin modem

The key point here is that every standard requires a lot of effort to enable a strong eco-system that can support design, verification, testing, production. The devices referenced above are examples of collaboration between many companies which allow to support these interfaces on the mobile devices we use today.

And some very important things that are sometimes neglected:
1. prototyping system that allows to validate design functionality and develop the IC and system around it prior to taping out or receiving silicon back
2. interoperability with devices commonly found in the market to avoid failures in the field

Covering these two points is illustrated in the diagram above and video we prepared that shows DigRFv4 implementation for baseband processor connecting with off-the-shelf RFIC.
So next time you consider to adopt a standard do check if a prototyping platform is available and if interoperability was tested, this will save you a lot of effort, remove risk in adopting the new standard. In other words Synopsys assists in speeding time-to-standard.

Last on a more personal note:
I don’t know if TTS was coined already for Time-To-Standard, I’m aware of TTS with reference to Text-to-Speech as I was the marketing manager for the single-chip SoC supporting text-to-speech algorithm. See datasheet of this SoC here in case you’re interested in this ~10 year old technology from ISD/Winbond.

 

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Posted in Baseband processor, DigRF, LLI, M-PHY, MIPI alliance, RFIC, Smartphone, SoC, Tablet | Comments Off

Use of UFS Host and UniPro in a typical system

Posted by Hezi Saar on October 9th, 2012

 

I was approached by many readers asking for more information about integration of UFS in their SoC platform. As the information provided on the Synopsys MIPI web site gives you a good overview of the Synopsys UniPro controller and UFS Host controller it does not give you the high level view of what is delivered or what you need to integrate the Analog and Digital components in your SoC or storage IC.
We have another resource for you, please reference this article: Building High-Performance Interfaces for Storage, Camera and Displays Using UniPro and UFS Controller IP which gives you an overview of our M-PHY, UniPro, UFS solutions, illustrating how they are used in a semiconductor environment and also provide some details about our FPGA prototyping platform to enable your system prototyping requirements.

If any of you plan to be at the MIPI Alliance F2F in Miami next week, our team of experts will be there to demonstrate some of our latest solutions in action and answer your questions.

 

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Posted in Application processor, Camera, CSI, Display, DSI, M-PHY, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

UFS, UniPro and You

Posted by Hezi Saar on September 23rd, 2012

JEDEC UFS (Universal Flash Storage) v1.1 is a standard promoted by JEDEC JC64.1 aiming to replace eMMC for scalable and high performance non-volatile memory interface in mobile and consumer electronics. The same JEDEC JC64.1 is the group that develops eMMC meaning that they see the transition from eMMC to UFS and are prepared to that. It’s fair to assume that UFS will be used in high end mobile applications first like high end smartphones, tablets and Ultrabooks and compete with eMMC on some of the lower end applications. Long term and assuming high volume manufacturing reduces UFS device costs we will see UFS replacing eMMC but there is a long way to go until we reach that time.

Here’s a forecast from iSuppli showing the growth expected in eMMC. You can assume UFS shipment start in 2013 and 2014 in low volume and ramping rapidly starting 2015, which could explain the lower growth expected for eMMC in 2015.

UniPro

MIPI Alliance promoted UniPro (Unified Protocol) as the ultimate implementation of application agnostic layer removing the complexity of link reliability, retransmissions, hand-shaking from the application implementation. On one side the UniPro controller connects to MIPI M-PHY (via standard RMMI interface) that is responsible for the serialization of the data and transmit/receive of the signal to the IC on the other side of the PCB connection. To the SoC side, the UniPro controller offers standard write and read interfaces (through what the spec calls C-Ports) to send/receive data to/from the remote device and configuration interface (called Device management entity – DME) to configure all the UniPro layers such as Transport, Network, Data Link and PHY adaptation. These Write, Read and Control interfaces simplify the connection to different applications and takes care of the complexity associated with high speed data transmission reliability. The first application layer that used today is UFS that uses the UniPro controller to implement the JEDEC UFS v1.1 standard. Other applications using UniPro are MIPI CSI-3 and DSI-2 for next generation image sensors and embedded displays that plan to use MIPI M-PHY and UniPro.

  • You (the designer)

Pressure to meet demand for higher speed, lower power implementations coupled with new standard introductions are difficult to meet. Using these low risk UFS and UniPro controllers with the Synopsys future-proof M-PHY can simplify and help new protocol adoption. Building on these standard IP blocks, You can focus on differentiating features that will help make the product more competitive in the market.

I don’t have a picture of You here but if it’s not too difficult You can look in the mirror. In case you don’t have one handy then look at this funny image about engineers and maybe you’ll find yourself in the picture.

More resources to explore the Synopsys UFS and MIPI IP:

DesignWare® MIPI IP web page

DesignWare® UFS Host Controller IP web page

DesignWare® MIPI UniPro Controller IP web page

DesignWare® MIPI M-PHY IP Web page

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Posted in Application processor, Camera, CSI, Display, DSI, Image signal processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

Office gone Mobile

Posted by Hezi Saar on August 30th, 2012

The world continues to change in front of our eyes. The things that were considered essential a decade ago are now obsolete.
Latest research from Virgin Media Business suggests that Landline phones in offices will be replaced by smartphones. The research says that 65% of the Chief Information Officers interviewed said that the desk telephone is likely to become redundant while the dominance of smartphone grows.
Furthermore, 62% of the CIO’s that were interviewed pointed out that also desktop computers are the next item to disappear from the office.

What will we be doing then? As always technology advancements allow us to increase productivity and have an easier and better access to information. Laptops, Ultrabooks provide a good alternative to desktops with the convenience of portability. Smartphone provide the ability to be reached everywhere.

Here’s a nice picture showing in a funny way how technology changes and makes you wonder about the increasing rate of change:

If you want to read more about this survey, follow this link.


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Posted in Application processor, Baseband processor, Smartphone, SoC, Tablet | Comments Off

The Need for Speed – D-PHY

Posted by Hezi Saar on July 28th, 2012

I cover topics about low power and mobile applications in the past years but there is something that is often neglected. It comes at the expense of lowering the power and it is performance. We can argue that minimizing power consumption is dependent on what kind of power we’re reducing (for example static or leakage vs. dynamic power) and its effect of the performance but we know that there is no void in physics and Higher Voltage threshold for example reduces leakgae but affects max performance.
The problem we have is that as much as we need lower leakage power and lower dynamic power to prolonge the battery life between charges, we also need high performance as we don’t want to wait for an application to load itself or transfer data to our mobile device.
As part of my role I track the operating performance of Image sensors and Displays and one of the good measurements is the maximum bandwidth used by the camera interface CSI-2 and display interface DSI.
I discussed this with David Wolfe (reference my interview with David here) and he provided me some statistics observed as part conducting interoeprability events in the past years.

The first diagram below shows the average speed per lane at each of the past 4 MIPI Display Interop Workshops. It gives us an interesting snapshot of the progress of MIPI DPHY devices, and we see that the speed per lane is steadily increasing.

The second diagram shows the average throughput of each device at the last 4 MIPI Display Interop Workshops. In this case, throughput is simply Mbps per lane times the number of lanes. You can see at the 2012 event throughput took a big jump ahead, largely due to the number of 4 lane devices.

It shows us an interesting trend in the type of demand that exists for MIPI DPHY displays that newer displays use higher bandwidth to achieve higher resolutions.
That’s not a surprise by any mean and we see this in the mobile devices exist in today’s market. What is means is that if you are developing an SoC and target to connect to cameras and displays, you better have flexibility in the maximum number of lanes supported to cover both low and high resolution cameras and displays. In addition you need to select carefully the IP you’re using and for your 28nm SoC design support for the 1.5Gbps possible with the D-PHY v1.1 specification is highly desired. Check out this page for more information about D-PHY capabilities covering performace up to 1.5Gbps/lane.


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Posted in Application processor, Camera, CSI, D-PHY, Display, DSI, Image signal processor, MIPI alliance, Smartphone, SoC | 2 Comments »

CSI-2 and DSI Hardware demo at Mobile Expo 2012

Posted by Hezi Saar on June 27th, 2012


We participated at Mobile Expo as part of the MIPI alliance booth and had hardware demonstration showing our complete and interoperable CSI-2 and DSI host interfaces.

Here’s a block diagram of the demo which shows a complete CSI-2 images sensor interface and DSI display interface that Application processors can use to quickly integrate and prototype this solution in their design.

The block diagram shows a complete CSI-2 interface (comprising of D-PHY optimized for CSI-2 host application and CSI-2 host controller) connecting to a microcontroller that extracts the image and places it in package for trasmission through the DSI interface (comprising of DPHY and DSI host controller).

We continue investing in building complete and interoperable solutions to help semiconductor designers adopt new standards while lowering design risk and meeting time to market challenges. I will share more information about other standards in the coming weeks. Please stay tuned.


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Posted in Application processor, Camera, CSI, D-PHY, Display, DSI, Image signal processor, MIPI alliance, Smartphone, SoC, Tablet | Comments Off