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UFS and CSI-2 Accelerated Design

Posted by Hezi Saar on November 19th, 2014

With the rumors about UFS going mainstream with first introduction in Samsung Galaxy S6 phone expected next year (2015), I wanted to raise what I see as a repeat concern when discussing adoption of new standard (such as UFS).
A key challenge in today’s mobile IC and electronics design is the ability to meet time to market window, get your system up and running with new standards and interoperate with other devices. This is particularly true for JEDEC UFS v2.0 which is fairly new standard that the indusrty is gearing up to mass production of the first UFS devices and Application Processors targeted to be available in the hands of customers in 2015.

Availability of a mature, low risk IP from a reputable company is critical to achieve these goals. I met with too many customers that chose an IP that is claimed to be available or lower-cost to realize at the end that they have no product to go to market with. A big part of the IP selection critera is having a prototyping system that puts hardware and software together and provides a complete system.

You can see our UFS complete solution demonstration here:

JEDEC UFS and MIPI CSI-2 are very good examples to such a system that provides a complete vertical solution to customers developing Mobile ICs. Having MIPI CSI2 and UFS IP prototyping kits enable customers to have an immediate access to proven solution that can easily connect to other external devices and serve as out-of-the-box reference design.

Here’s a video showing USB3.0 IP Prototyping kit, so that you get the idea:

With availability of a variety of proven protcols (USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0, and JEDEC UFS) I see many benefits to the industry by allowing vendors to explore new concepts before their IC design starts, enabling rapid connectivity and starting the hardware design at a later stage. IP Prototyping kits can also help in interoperability tests, in software development while the hardware is being worked on (designed, fabricated, characterized) so more things can be done in parallel and achive the increasing time to market pressures.

Come and get you IP Prototyping kit, read more here.


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Posted in Application processor, Camera, CSI, D-PHY, Display, DSI, Image signal processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | No Comments »

Demand your M-PHY

Posted by Hezi Saar on January 27th, 2014

MIPI Alliance’s M-PHY specification v3.0 provides a solid specification targeted to a variety of applications in the mobile electronics space. I hear some concerns about that this technology is new and engineers prefer to wait for the adoption to pick up before they use it.

Well, it is true that MPHY v3.0 specification is about 1 year old, however note that the M-PHY v1.0 specification was introduced about 3 years ago and was first adopted in DigRFv4 applications. There are several IC’s using M-PHY in production, here’s an example of a Fujitsu Baseband processor. The foundation of the circuitry for higher gears and features introduced in MPHY v3.0 were already established and used several years ago. Furthermore, MPHY v3.0 spec is used by several protocols including those defined by the MIPI alliance work groups (such as UniPro, CSI-3, LLI, DSI-2) and those adopted by other standard bodies which selected the MIPI M-PHY as the physical layer for these applications.
The standard bodies that adopted M-PHY are an industry recognized and established organizations such as USB-IF (promoting USB3.0 SSIC over M-PHY), PCI-SIG (promoting MPCIe over M-PHY) and last but not least JEDEC (promotion UFS over M-PHY).

I sometime get asked about my prediction about M-PHY adoption.
I recently read an interesting article about time travelers. It would have been nice to be able to time travel and accurately predict technology trends (not to say buy a winning lottery ticket), however since I don’t have that talent (yet) I have to rely on my knowledge and thoughts.
I don’t have a crystal ball. However, I am certain that M-PHY v3.0 presents an inflection point in the mobile market which strives for low power, scalable physical layer to build highly optimized architectures in the mobile electronics market.

There is a lot to do in order to build M-PHY as a winner. At this time we have to rely on our judgment and what we know as facts. You can educate yourself more about the M-PHY technology by reading the technical whitepaper recently published. It is a very good read and covers the major topics M-PHY technology is trying to solve.
You can also access the On-Demand recorded webinar at Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP.

Last, I would love to meet with you and discuss further. I plan to be in Mobile World Congress 2014 in February, feel free to send me an email or leave me a message/comment below and we can arrange something.


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Posted in Application processor, Baseband processor, Camera, DigRF, Display, DSI, LLI, M-PHY, MIPI alliance, Mobile PCIe, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

Demonstating M-PHY v3.0 Silicon

Posted by Hezi Saar on June 7th, 2013

MIPI M-PHY is a promising technology, intesnded to be used across multiple applications and utilized by standard organizations such as JEDEC for UFS, USB for SSIC, and PCI-SIG for Mobile PCIe. We have been working in the past several months to develop and prove M-PHY in HS-Gear3 operation as the specification evolves in the MIPI PHY Work group. Our deep involvement in the group allowed us to develop the M-PHY which is fully compliant to the latest M-PHY v3.0 specification. In March 2013 during the MIPI Face-to-face meeting we demonstrated M-PHY operation in HS-Gear3 and showed it to everyone on the floor. I recevied a lot of requests to share the video of this demo and now it is ready.

Here are some measurements taken live using the Tektronix equipment connected to the Synopsys M-PHY.

And here you can see the video and the measurements taken at the Transmitter and using loopback mode.

We will be at the next MIPI F2F meeting in Warsaw if you have further questions for me or the MIPI team.


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Posted in Application processor, Baseband processor, CSI, DigRF, LLI, M-PHY, MIPI alliance, Mobile PCIe, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

Meeting power, performance and reusability requirements for mobile systems

Posted by Hezi Saar on April 16th, 2013

Discussing and sharing opinions is what drives our industry forward; however sharing ideas becomes more challenging in our time where competition is intense. This is true for any industry but even more relevant to the high-pace mobile market where wrong move can cost you a fortune. It is that important then to stay connected and aligned with market trends so you’re not caught off guard and mitigate design and market risks while enabling to take a leadership position.

I’ll be at the Linley Mobile conference which starts tomorrow (April 17 2013) and will be speaking on Thursday April 18th, during the Power-Optimized Design session which starts at 2:35pm, about meeting power, performance and reusability requirements for mobile systems. I will specifically address the growing needs in high performance and mobile-friendly interfaces for chip-to-chip communication such as USB3.0 SSIC and Mobile PCI Express.

These interfaces address the growing needs in higher data throughput transmitted between devices and allow the re-use of existing infrastructure while delivering mobile-friendly solution.

It’ll be good to see you, share ideas about your next design needs and discuss alternative paths.


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Posted in Application processor, CSI, D-PHY, Display, DSI, LLI, M-PHY, MIPI alliance, Mobile PCIe, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

Shifting to High Speed Gear 3

Posted by Hezi Saar on March 15th, 2013

The MIPI alliance announced the release of M-PHY v3.0 in Barcelona which solidifies the Gear3 and other specs enhancements. From the press release I can quote this:
M-PHY® v3.0 delivers a low-power, scalable physical layer with a data rate range nearing 6Gbps. CSI-3 has been adopted and is available for MIPI Alliance members. LLI v2.0 and M-PHY® v3.0 are scheduled for adoption by the end of April 2013.

Synopsys launched the Industry’s first Multi-Gear M-PHY supporting Gear1, Gear2, and Gear3 which makes it future proof for new protocols back in February 2012. And in the meantime we are contributing to the M-PHY v3.0 specification as we were driving previous specifications.

Next week during the MIPI F2F meeting in Asia (demo day on March 19th), Synopsys will be demonstrating the First silicon proven M-PHY operating at High Speed Gear3 and connecting to Tektronix test equipment.

This demo shows Synopsys true leadership in driving the M-PHY v3.0 specification in the MIPI alliance PHY Work Group in parallel to IP development which allows us to be first to market and first to silicon at the time of final specification.

As M-PHY becomes a popular physical layer for many applications, we continue to see applications adjacent to mobile that would like to use it. I can quote another piece from the press release:
In addition to supporting smartphones and full-function phones, these MIPI specifications are suitable for other applications that require low power, high bandwidth – including tablets/netbooks, consumer electronics, high speed memory storage, automotive and portable medical devices.

See you next week in MIPI F2F meeting, and come see our Gear3 M-PHY demo.


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Posted in Application processor, Baseband processor, Camera, CSI, DigRF, Display, DSI, LLI, M-PHY, MIPI alliance, Mobile PCIe, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

Design for Phablets

Posted by Hezi Saar on March 6th, 2013

I spent last week at Mobile World Congress 2013 in Barcelona, where Synopsys also demonstrated our D-PHY, CSI-2 and DSI protocols running in hardware and connecting to Agilent test equipment and UNH conformance test suite.

I also gave a short presentation discussing the challenges designers face when designing SoC’s for use in mobile electronics such as media phones, smartphones, tablets and ultrabooks, or maye as a portmanteau Phablet.
The presentation covered the interfaces commonly found in Phablet SoC’s (I’m starting to like this portmanteau…) and the convergence I believe is driven by the common use cases as well as design and manufacturing costs that have to be amortized across many applications.
In addition to cable connection like USB, HDMI or MHL, the SoC supports a variety of interfaces ‘in-the-box’ such as embedded displays, image sensors, storage, and chip-to-chip connectivity to wireless ICs, Baseband or RFICs.

Synopsys’ efforts in delivering IP for Phablets include providing future proof and silicon proven IP and also working with device vendors to achieve interoperability which is very important for new standard adoption.
A good example of interface convergence is the use of M-PHY and the unique position Synopsys has in delivering silicon proven HS-Gear3 M-PHY for customers who wish to adopt a variety of M-PHY based protocols like JEDEC UFS, MIPI UniPro/CSI-3, USB3.0 SSIC and M-PCIe. This implementation allows most flexibility in achieving lowest total power, supporting latest progression of protocols, and promotes IP re-use.

Stay tuned for more news next week.

[this post was edited on March 12, 2013]


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Posted in Application processor, Baseband processor, Camera, CSI, D-PHY, DigRF, Display, DSI, Image signal processor, LLI, M-PHY, MIPI alliance, Smartphone, SoC, SSIC, Storage, Tablet, UFS, Unipro | Comments Off

JEDEC UFS v1.1 in Silicon

Posted by Hezi Saar on February 8th, 2013

Toshiba’s launch of the Industry’s First Embedded NAND Flash memory module compliant with JEDEC UFS v1.1 marks an impressive milestone for the mobile storage market space.

This memory is capable of driving 2.9Gbps compliant with M-PHY Gear2 Rate B and these samples are intended for evaluation by SoC and OS vendors. JEDEC UFS v1.1 is based on MIPI UniPro and MIPI M-PHY and implements functions compatible with eMMC v4.51 but include protocol improvements such as usage of SCSI Command set, Command queueing, Context ID and Data tagging which enable higher performance.

Synopsys is also first in UFS (and UniPro), back in October 2012 we have demonstrated interoperability between our UFS Host solution in Hardware connecting to (yes, you guessed right) Toshiba UFS device hardware implementation. Both solutions are compliant to UFS v1.1. See video here:

Being first to market can’t be a bad thing. The “first mover advantage” is actually a key parameter that determines the business success in the long run. Assuming JEDEC UFS standard becomes popular, the next inflection point in the market where other Storage vendors could catch up is when JEDEC UFS v2.0 is introduced. This is why we are an integral part of the JEDEC UFS work group, MIPI UniPro work group and MIPI PHY workgroup and sub-groups where important decisions about the specification take place.


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Posted in Application processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

First JEDEC UFS v1.1 Host and Device Interoperability

Posted by Hezi Saar on December 13th, 2012

I want to share a video showing the work we are doing at Synopsys to help semiconductor vendors adopt the JEDEC UFS v1.1 standard needed for high performance storage applications. Thr video shows the Synopsys UFS Host solution connecting with the Toshiba UFS Device prototyping platform and operating a sequence of read and write commands. These commands are sent from the host to the device to store and fetch the data from on-board NVM using the UFS link. As you can expect we have done more comprehensive interoperability tests beyond that.

The interoperaiblity test was done back in October 2012 and it is the first UFS Host and Device interoperability between a ‘host’ company (Synopsys) and a ‘device’ company (Toshiba). What does it mean to be first to demonstrate system level interoperability of this new JEDEC UFS standard?
It means we have a complete and working solution, we can demonstrate it, we can license our proven IP to potential semiconductor vendors who want to adopt UFS v1.1, we can support customer’s hardware prototyping needs and we help reduce the risk of adopting the new UFS standard by conducting these interoperability tests with UFS device vendors.
It means we have a mature solution that can be used today for SoC’s that want to adopt the JEDEC UFS standard.

We (Synopsys) continue to invest in creating a healthy and robust eco-system by driving these mobile electronics standards in JEDEC and MIPI alliance and conducting interoperability tests with device vendors.
Want to learn more about UFS implementation? here’s a nice article that you can read and here’s a joint webinar between MIPI Alliance and JEDEC that will give you a good overview. For those who like to read specifications, here’s a link to a free download the UFS v1.1 spec.


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Posted in Application processor, Image signal processor, M-PHY, MIPI alliance, Smartphone, SoC, Storage, Tablet, UFS, Unipro | Comments Off

DigRFv4 System Demo

Posted by Hezi Saar on November 8th, 2012

Mobile devices that use baseband processors and RFIC’s require a lot of effort to integrate these componenets together in a very challenging environment: small and slim board, tight casing, lots of RF components that may cause noise. Adding to that integrating new interface between the baseband processor and RFIC makes this integration work even more difficult. Synopsys can assist and reduce the integration risk and interface adoption easy for those who selects to integrate this kind of interface, namely the DigRFv4.
Here’s a short video that demonstrates our integration effort with hardware prototyping system that emulates the baseband processor DigRFv4 interface and connects to Fujitsu RFIC hardware system.

This demonstration shows the data flow from baseband to RFIC and back. If you are considering to use DigRFv4 interface in your next design this setup demonstrates proven system-level interoperability that reduces unknowns of the design.


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Posted in Baseband processor, DigRF, LLI, M-PHY, MIPI alliance, RFIC, Smartphone, Tablet | Comments Off

TTS: Time-To-Standard

Posted by Hezi Saar on October 30th, 2012

It takes time to bring a standard solution. Starting from a problem, idea, collaboration and specification to a standard use in the market. It takes a very long time to build an eco-system around a new standard and have it proliferated in many designs.
Lets take DigRF spec for example and quickly look at the history. DigRF was established as a MIPI Alliance work group in April 2007. The goal was to develop a specification that will standardize the interface between baseband processors and RFIC’s for existing and future air traffic standards such as 2.5G, 3G, LTE and LTE-Advanced. DigRF 3G was the first specification released that addressed the dual mode 3GPP-compatible 3G /2.5G (UMTS/EGPRS) implementations and later extended to later versions of 3G. In July 2008 the DigRF 3G v3.09.04 specification was approved for release to MIPI members. This specificaiton saw some implementations but was not future-proof for higher bandwidth air links so naturaly that limited the adoption.

DigRFv4 interface was specified to target the continuous increase in air links bandwidth, demand for higher channel bandwidth, IQ sample rates and bit width, RX diversity and MIMO. In addition DigRFv4 aimed at standardizing the link between baseband and RFIC and use a scalable physical layer for that purpose as the work group envisioned the demand for higher bandwidth. DigRv4 is the first protocol that used the MIPI M-PHY due to its scalability, low power and low EMI capabilities.

In May 2010 the DigRFv4 v1.00.00 spec was approved and those vendors who were embedded in the work group and already worked on the implementation started releasing their products to the market. Here’s a link to a public release made at that time: Synopsys claims industry’s first MIPI DigRF v4 IP. And a release of DigRFv4 v1.10 spec followed this year: MIPI® Alliance Advances Radio Frequency Interface Technology in Mobile Devices.

Today we see a selection of baseband processors and RFIC’s that use this DigRFv4 interface, here are a few examples of RFIC and baseband processor solutions:
* Fujitsu RFIC
* Sequans baseband for LTE
* Marvell LTE thin modem

The key point here is that every standard requires a lot of effort to enable a strong eco-system that can support design, verification, testing, production. The devices referenced above are examples of collaboration between many companies which allow to support these interfaces on the mobile devices we use today.

And some very important things that are sometimes neglected:
1. prototyping system that allows to validate design functionality and develop the IC and system around it prior to taping out or receiving silicon back
2. interoperability with devices commonly found in the market to avoid failures in the field

Covering these two points is illustrated in the diagram above and video we prepared that shows DigRFv4 implementation for baseband processor connecting with off-the-shelf RFIC.
So next time you consider to adopt a standard do check if a prototyping platform is available and if interoperability was tested, this will save you a lot of effort, remove risk in adopting the new standard. In other words Synopsys assists in speeding time-to-standard.

Last on a more personal note:
I don’t know if TTS was coined already for Time-To-Standard, I’m aware of TTS with reference to Text-to-Speech as I was the marketing manager for the single-chip SoC supporting text-to-speech algorithm. See datasheet of this SoC here in case you’re interested in this ~10 year old technology from ISD/Winbond.

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Posted in Baseband processor, DigRF, LLI, M-PHY, MIPI alliance, RFIC, Smartphone, SoC, Tablet | Comments Off