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Magic Blue Smoke
  • About

    Magic Blue Smoke is a blog dedicated to discussing the challenges of low power ASIC Design

    I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/
    multi-supply designs. The goal of this blog is to open a free exchange of ideas with regards to low power. Please participate!

    - Godwin Maben

Archive for the 'Infrastructure' Category

Physical Structure of Special Cells

Posted by Godwin Maben on 26th August 2008

Today let me give a quick insight into various special cells and their physical structure

(a) Level Shifters: In general there are 3 types of Level Shifter.

(i) High2Low LS: Shifts the Voltage from High 2 Low. Physically these are single row height cells and have 2 rails VDD and VSS. Conceptually they are nothing but high drive buffers and nodes gets charged upto the VDD(low), even though input is driven from higher voltage source. One of the key requirement for this kind of cell is they got to be placed in Lower Voltage Domains.

(ii) Low2High LS: Shifts the Voltage from low to high. Physically these are 2 row height cells and has 3 rails, Primary VDD(Low), Secondary VDD(High) and VSS(Ground). Ideally these are placed in Lower Voltage Domains.

(iii) Generic LS: These cells can shift the voltage in either direction. They are generally used in designs that deploy DVFS technique. Physically these are 2 row height cells.

(b) Isolation Cells: In general there are 3 types of Isolation cells.

(i) Simple Isolation Cells: Physically these are single height cells
(ii) Enable Level Shifters: These are combination of a Isolation cell and Level Shifter. Physically they are similar to level shifter explained above
(iii) AON Isolation cells: These are dual rail cells, physically these are 2 row height cells and has 3 rails, Primary VDD(ON/OFF VDD), Secondary VDD(AON VDD) and VSS(Ground)

I will discuss about the other special cell’s physical structure in my next post tommorrow.

Posted in Infrastructure | 6 Comments »

Infrastructure Needs for Multi-Voltage Designs

Posted by Godwin Maben on 11th April 2007

Before we start looking at implementing a Multi-Voltage design there are certain questions we need to find out from process/library perspective such as

  •  Available Operating Voltages(PVT)
  • Do we have special cells such as Level Shifters/Isolation cells/Power Gating Switches ?
  • If Level Shifter exists, what kind of level shifters are available? (ex: Enable Level Shifter..etc)
  • What are the different corners that need to be used for sign-off?
  • How should we handle OCV?
  • How accurate are these timing models? Is NLDM good enough or do we need CCS/ECSM models?
  • Do we have special cells with Dual Rails(ex: Retention Flops)? If yes How is the timing captured for each rails?
  •  Are these cells characterized for Power, do they have State Dependent Path Dependent Information?
  • If special cells exists, is it modelled according to EDA tools requirement?
  • For Feed through implementation, do we have special Always On Buffers ? What’s the impact of routing the secondary power pins of these buffers on routing resources?
  •  Given range of Operating Voltages, is there an easy way at early stage of implementation cycle to judge on right Voltage selection? (power/performance product)
  •  Am I getting required power savings by implementing the design in Multi-Voltage style?  For ex. If number of special cells required to implement this are too many, is it worth the effort? Can we look at an alternate way of saving power?
  • Just to give an example , recently for one design I found out that around 26K Level Shifters were required to implement a block and this has an adverse effect on power. But we did not have a choice as this was the best possible Voltage that met the required timing/power specification.

    Posted in Infrastructure | No Comments »