Archive for the 'implementation' Category

Today let’s look at the various structural errors or bugs that can be really destructive for any MV design. Structural error is a bug, which is caused either by, the way RTL is written or implementation tools interpreting the power intent incorrectly. These can be further classified as structural errors leading to electrical violations or structural errors leading to pure functional failures. Given below are some of them

(a) Placement of Buffers in wrong location
(b) Level Shifter Missing
(c) Isolation cell missing
(d) Wrong Isolation Polarity
(e) Using LS+ISO instead of Enable Level Shifter
(f) Normal Buffer instead of AON buffer being used
(g) AON buffers with single rail placed in non-power able region
(h) Placement of Special Cells in wrong location
(i) Connection of Switch cells
(j) Connection of all dual rail cells not aligned with proper power strategy
(k) Power/Ground Net Connectivity for Islands
(l) Redundantly Retained and Not Retained.
(n) Retention Reach ability
(o) Retention Flops wrong polarity
(p) Unsafe Voltages
(q) Incorrect Clamp Values
(r) Wrong Tie-Hi and Tie-Lo Connections
(s) Isolation Enable reaching Data pin of Isolation cell
(t) Rail Order Violations for islands

Lets take a look at various low power techniques in use today.I would classify the various low power techniques into 2 categories

(a)Structural Techniques

(b)Traditional Techniques

Which one of the above techniques are aimed at reducing Dynamic Power and Leakage Power

Dynamic Power Reduction

Leakage Power Reduction