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Magic Blue Smoke
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    Magic Blue Smoke is a blog dedicated to discussing the challenges of low power ASIC Design

    I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/
    multi-supply designs. The goal of this blog is to open a free exchange of ideas with regards to low power. Please participate!

    - Godwin Maben

Low Power Static Checks

Posted by Godwin Maben on August 12th, 2010

There seem to be some confusion about types of checks that need to be performed on a Low Power Design. In the Low Power static check world, following 3 types of analysis can be done on a design, in addition to various other checks.

(a) Critique Check

    Power State Table is Golden here and design structure is validated for correctness based on this table. For example “ Compare the ISO/LS elements present in the design with the ISO/
LS requirement inferred by analyzing the PST”

(b) Power Intent Check

Design is validated as per the Power Intent provided by user, here Power State Is ignored and mostly user written rules/policies are considered while checking, design structure is validated against user written policies  for correctness.

(c) Low Power Architecture Checks

Here design is analyzed for any architectural failures with respect to the requirement specified in the power intent. For example: Checking Power Up and Power Down Sequences of various power domains, checking for reachability of control and clock paths to the design.

3 Responses to “Low Power Static Checks”

  1. In opinion we need to get out of the low level power optimizations. These low level optimizations contribute less than 10% of power savings. The major power reduction can happen only at the architectural levels and software level. For example
    multicore RISC architecture is better than a VLIW processor, where the power is consumed in every cycle switching wide Instruction buses. This decision can only be made by the engineering teams or system architects (also look at SIDO architecture for low power). Similarly, at the software level, the data structures should be partitioned in such a manner that minimum external memory references are made, this can be performed by a smart compiler.

  2. Abhinav says:

    Great blog, you have made very interesting posts. Do keeo posting on various aspects related to UPF spec.

    @Aamir: Though architectural tradeoffs are important, I believe low level optimizations can be complementary to high level techniques. For eg, the algorithm can dynamically determine based on the input that certain portions of the chip are not going to be used and turn them off using the low level switches/control logic.

  3. IC Design is the base of all the computing processes.