Interesting Low Power Sessions at SNUG Sanjose 2010
Posted by Godwin Maben on March 26th, 2010
Monday, March 29, 2010
11:00 AM – 12:30 PM
MA1 Tutorial : Implementation
PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
MA2 User – Constraints and Power Challenges in Verification : Verification
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster
Monday, March 29, 2010
1:45 PM – 3:15 PM
MB3 Tutorial : AMS
HSIMplus CircuitCheck for Low Power Transistor Level Error Detection
Power Correlation with Silicon – A PrimeTime PX Evaluation
Tuesday, March 30, 2010
10:15 AM – 11:45 AM
TA1 User –
Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
TA2 Tutorial : Verification
Low Power Verification
Tuesday, March 30, 2010
1:00 PM – 2:30 PM
TB1 User – Implementation
LeSa Lowers Leakage
Tuesday, March 30, 2010
2:50 PM – 4:50 PM
Clock Power Reduction-Analysis Metrics and Power Reduction Techniques
Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF) Standard
Wednesday, March 31, 2010
10:15 AM – 11:45 AM
WA1 Tutorial : Implementation
Energy Efficient Processor Implementation with Synopsys’ Eclypse Low Power Solution
WB5 Tutorial : IP
Extreme Low-Power Datapath Design with DesignWare minPower Components










I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/
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