Posted by Godwin Maben on March 18th, 2010
Again sorry for the long break in writing, wish I could write at least one post per week,
Recently based on some silicon debugging, we realized verification did not cover some aspect of the power down function that lead to chip failure. Later realized that, this is being mentioned some where in VMM LP manual, thought of sharing this here.
MOS transistors are dependent on their gate-source voltage difference to determine whether they are “on” or “off”, also known as “conducting” or “non-conducting”. This mechanism is used in power gating. The Gate voltage is such that the transistor is non-conducting. This is done by issuing logic “1” to the Gate, which charges it up to the Vdd level of the driver. In general, this is the same voltage level as the power switch. The gate-source difference kicks in to turn the transistor off. However, when the Vdd of the power gating signal’s driver “dips”, the off island makes an “on” excursion and come back. On the other side, the power gate can also become more resistive. Similarly, an on island with a footer can suddenly become more resistive or make an on excursion.
This phenomena is quite dangerous, as it will lead to a current spike and a further collapse of rails. Although the profile looks like a power integrity issue and may well be caused by bad implementation of the power grid, frequently the cause is an over-scheduling of power state changes instead of staggering them in time. This in turn causes fluctuations in the power supply. The Power Management Unit must take the stability of the power supplies into account before moving rails in voltage value.
Will talk on the verification plan for this scenario in my next post.