Archive for October, 2009

Isolation cells are used in almost all power gated designs.  Given below are some tips about these cells, this information is based on my experience working with various designers.

 (1) Output signal isolation is usually a better choice than the input isolation .

(2) Input isolation is reasonable on designs that have controllable independent power domains

(3) If custom isolation cells are not available, regular cells such as (AND/NOR) can be used, but we need to make sure that these cells are kept alive all the time.

(4) Isolation cells impacts timing and area and hence should be used and analyzed properly. It should be inserted as early as possible in the design cycle to account for area/timing penalty.

(5) If feed through paths exist in the power down domain, its not necessary to isolate these nets , but need to be kept alive

(6) Isolation cells should be placed close to boundary and interface nets should be protected all the time and should not be buffered if its residing in a domain, whose power characteristics is different from source/sink domain

(7) Some logic cells such as XOR gates, should be avoided at the interface logic so as to prevent any accidental sneak paths

(8) Check the isolation states to make sure, parking at one value “1” or “0” does not lead to any sneaky paths

(9) Its preferable to use enable level shifter instead of LS+ISO cells .

(10) Last but not the least, make sure to write the isolation policy in UPF at the right interface. Its not practical and reasonable to write isolation policy both at the sink/source simultaneously.

Lets discuss about the placement of these cells and AON’ness of these cells in the next post.

My apologies for changing the title of my previous post. I realized that most of the optimization challenges are primarily due to the design requirements not UPF requirements. UPF is just a medium to define power intent, similar to verilog defining the logic intent of the design.

continuing on the same topic, few more reasons, which makes optimization challenging are

1. Isolation cells, isolating off/on blocks need to be placed closer to source if the isolation cell used is a single rail cell and its residing domain is different than the source/sink domain. This ensures that the signal is isolated properly to reach the sink. Scenario changes if the isolation cells used are dual rail isolation cell. 
2. During scan mode, all the special cells should be directly controllable and observable . This puts restriction on how tools can handle scan chain. This can also lead to scan chain re-ordering locally.
3. Global signal distribution need to be power aware.. This leads to proper usage of AON buffers and regular buffers depending on how the global signal traverses.
4. Physically each power domain/island/voltage area can restrict the routing of the signals, which might lead to taking  longer route to reach destination. Due to these longer routes, more buffers/inverters/logic may be required to fix transition/timing/si requirements.