Archive for November, 2008

Today let’s look at the various structural errors or bugs that can be really destructive for any MV design. Structural error is a bug, which is caused either by, the way RTL is written or implementation tools interpreting the power intent incorrectly. These can be further classified as structural errors leading to electrical violations or structural errors leading to pure functional failures. Given below are some of them

(a) Placement of Buffers in wrong location
(b) Level Shifter Missing
(c) Isolation cell missing
(d) Wrong Isolation Polarity
(e) Using LS+ISO instead of Enable Level Shifter
(f) Normal Buffer instead of AON buffer being used
(g) AON buffers with single rail placed in non-power able region
(h) Placement of Special Cells in wrong location
(i) Connection of Switch cells
(j) Connection of all dual rail cells not aligned with proper power strategy
(k) Power/Ground Net Connectivity for Islands
(l) Redundantly Retained and Not Retained.
(n) Retention Reach ability
(o) Retention Flops wrong polarity
(p) Unsafe Voltages
(q) Incorrect Clamp Values
(r) Wrong Tie-Hi and Tie-Lo Connections
(s) Isolation Enable reaching Data pin of Isolation cell
(t) Rail Order Violations for islands

Its been quite some time since I blogged , I was on a vacation for last 3-4 weeks. Nice to be back again.

For next few posts, planning to talk through the verification challenges seen on a low power design.

First let’s try to classify various types of bugs that can be found in a multi-voltage/supply designs.

If we were to categorize them at a 10000ft level, it could be as simple as

(a) Structural Failures
(b) Control Sequence Failures
(c) Architectural Failures

lets look into each of one of them in subsequent posts.