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    Magic Blue Smoke is a blog dedicated to discussing the challenges of low power ASIC Design

    I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/
    multi-supply designs. The goal of this blog is to open a free exchange of ideas with regards to low power. Please participate!

    - Godwin Maben

Writing UPF for a DVFS design

Posted by Godwin Maben on August 18th, 2008

Often times I get questions on how to write an UPF describing the varying nature of Voltage in a DVFS design. I will try to explain how this can be done at a very higher level. If any one of you have any specific question please let me know so that I can elaborate on that.

Lets assume that the basic part of UPF is already written, most important statement here is how to build a PST that represents “V”.

Here is a PST with multiple power rails in a design.

add_port_state VDD -state {HV 1.08}

add_port_state VDDG -state {HV 1.08}
-state {LV 0.864}
add_port_state DVFS_VDD -state {-state {HighPerformance 1.08}
-state {MedumPerformance 0.864}
-state {OptimalPower 0.72}
-state {StandbyMemory 0.52}

add_port_state dvfs_sd/out -state {HighPerformance 1.08}
-state {MedumPerformance 0.864}
-state {OptimalPower 0.72}
-state {StandbyMemory 0.52}
-state {OFF off}

create_pst dvfs_pst -supplies {VDD VDDG DVFS_VDD VIRTUAL_VDD}
add_pst_state overdrive -pst dvfs_pst -state {HV HV OptimalPower OFF}
add_pst_state function1 -pst dvfs_pst -state {HV LV MedumPerformance StandbyMemory}
add_pst_state function2 -pst dvfs_pst -state {HV HV HighPerformance OptimalPower}
add_pst_state function3 -pst dvfs_pst -state {HV LV HighPeformance OptimalPower}

As you see from the above table, its very clear that 2 VDD’s “DVFS_VDD and VIRTUAL_VDD” are varied and operational VDD’s are defined as “1.08, 0.864, 0.72 0.52″

This needs careful constraining at the implementation tool level to get what you want. I will explain the commands and approach to be used at synthesis/back-end in my next posting.

2 Responses to “Writing UPF for a DVFS design”

  1. Yongfu says:

    Hi, can you provide a more detail description of the DVFS? I am interested to try out this technique. Thank you.

  2. Sahil says:

    Hi Godwin,

    Clearly, the UPF specification above can handle multiple voltages. Could you also shed some light on how does the frequency of the clock is changed dynamically for DVFS?