Archive for 2008

Today let’s look at the various structural errors or bugs that can be really destructive for any MV design. Structural error is a bug, which is caused either by, the way RTL is written or implementation tools interpreting the power intent incorrectly. These can be further classified as structural errors leading to electrical violations or structural errors leading to pure functional failures. Given below are some of them

(a) Placement of Buffers in wrong location
(b) Level Shifter Missing
(c) Isolation cell missing
(d) Wrong Isolation Polarity
(e) Using LS+ISO instead of Enable Level Shifter
(f) Normal Buffer instead of AON buffer being used
(g) AON buffers with single rail placed in non-power able region
(h) Placement of Special Cells in wrong location
(i) Connection of Switch cells
(j) Connection of all dual rail cells not aligned with proper power strategy
(k) Power/Ground Net Connectivity for Islands
(l) Redundantly Retained and Not Retained.
(n) Retention Reach ability
(o) Retention Flops wrong polarity
(p) Unsafe Voltages
(q) Incorrect Clamp Values
(r) Wrong Tie-Hi and Tie-Lo Connections
(s) Isolation Enable reaching Data pin of Isolation cell
(t) Rail Order Violations for islands

Its been quite some time since I blogged , I was on a vacation for last 3-4 weeks. Nice to be back again.

For next few posts, planning to talk through the verification challenges seen on a low power design.

First let’s try to classify various types of bugs that can be found in a multi-voltage/supply designs.

If we were to categorize them at a 10000ft level, it could be as simple as

(a) Structural Failures
(b) Control Sequence Failures
(c) Architectural Failures

lets look into each of one of them in subsequent posts.

Based on my interactions with many designers for the past few years, most common
techniques in practice/proven today are

(1) Power Gating (Majority)
(2) Static Multi-VOltage
(3) Dynamic Voltage Scaling
(4) Adaptive Voltage Scaling
(5) Back Biasing

But lately I am hearing about new techniques being tried to prepare for future technologies, some of them include

(a) Razor
(b) Vanilla Flavor of Asynchronous Design
(c) Source Biasing
(d) DVFS to meet performance requirement at 45 and below
(e) Useful Variation
(f) On-Chip Process Monitor, to adapt to varying PVT
(g) Active Leakage Power Reduction(dynamic power cutoff)

I would like poll our low power user community on how many of you are really looking at
validating any or all of the above?

last week we saw physical structure of LS/ISO cells. Today lets look at

(a) Retention Registers: These are typically either dual height cells or single height wide cells. They have Primary Rail and Secondary Rail. Primary Rail is switchable and Secondary Rail supplies power, when Primary Rail is off. They are typically placed in a shut-down region. One important factor is, Secondary Rail need not be of same potential as Primary Rail in ON state. Having a potential just enough to retain the state while primary is off would be the most efficient way to optimize leakage. Higher the Secondary Rail potential more will be the standby leakage current.

One of the biggest challenge in the design process is how can we automatically identify, number of registers in the switchable block to be retained? This could be done primarily based on the design architecture knowledge and also based on how fast one wants the switchable block to be up and running. Latter part can be automated in a way using some of the formal/property checking tools.

Other challenge is in verifying the functionality of Retention Register during functional simulation. Some of the verification challenges are listed below.

(i) Simulate Save/Restore Functionality.
(ii) Verify the functionality of ” When Save is asserted Secondary Rail is already active with the required potential”.
(iii) Verify the functionality of ” When Restore is asserted Primary Rail is completely ON”.
(iv) When Retention Register is in Save mode and if Secondary Rail drops(because of adjust block waking up) to a value below the required potential, how do we recover ?
(v) What if Save/Restore Lines are not treated as ALWAYS_ON ?

……etc

Lets look at the the other 2 important cells in the next post.

Today let me give a quick insight into various special cells and their physical structure

(a) Level Shifters: In general there are 3 types of Level Shifter.

(i) High2Low LS: Shifts the Voltage from High 2 Low. Physically these are single row height cells and have 2 rails VDD and VSS. Conceptually they are nothing but high drive buffers and nodes gets charged upto the VDD(low), even though input is driven from higher voltage source. One of the key requirement for this kind of cell is they got to be placed in Lower Voltage Domains.

(ii) Low2High LS: Shifts the Voltage from low to high. Physically these are 2 row height cells and has 3 rails, Primary VDD(Low), Secondary VDD(High) and VSS(Ground). Ideally these are placed in Lower Voltage Domains.

(iii) Generic LS: These cells can shift the voltage in either direction. They are generally used in designs that deploy DVFS technique. Physically these are 2 row height cells.

(b) Isolation Cells: In general there are 3 types of Isolation cells.

(i) Simple Isolation Cells: Physically these are single height cells
(ii) Enable Level Shifters: These are combination of a Isolation cell and Level Shifter. Physically they are similar to level shifter explained above
(iii) AON Isolation cells: These are dual rail cells, physically these are 2 row height cells and has 3 rails, Primary VDD(ON/OFF VDD), Secondary VDD(AON VDD) and VSS(Ground)

I will discuss about the other special cell’s physical structure in my next post tommorrow.

Often times I get questions on how to write an UPF describing the varying nature of Voltage in a DVFS design. I will try to explain how this can be done at a very higher level. If any one of you have any specific question please let me know so that I can elaborate on that.

Lets assume that the basic part of UPF is already written, most important statement here is how to build a PST that represents “V”.

Here is a PST with multiple power rails in a design.

add_port_state VDD -state {HV 1.08}

add_port_state VDDG -state {HV 1.08}
-state {LV 0.864}
add_port_state DVFS_VDD -state {-state {HighPerformance 1.08}
-state {MedumPerformance 0.864}
-state {OptimalPower 0.72}
-state {StandbyMemory 0.52}

add_port_state dvfs_sd/out -state {HighPerformance 1.08}
-state {MedumPerformance 0.864}
-state {OptimalPower 0.72}
-state {StandbyMemory 0.52}
-state {OFF off}

create_pst dvfs_pst -supplies {VDD VDDG DVFS_VDD VIRTUAL_VDD}
add_pst_state overdrive -pst dvfs_pst -state {HV HV OptimalPower OFF}
add_pst_state function1 -pst dvfs_pst -state {HV LV MedumPerformance StandbyMemory}
add_pst_state function2 -pst dvfs_pst -state {HV HV HighPerformance OptimalPower}
add_pst_state function3 -pst dvfs_pst -state {HV LV HighPeformance OptimalPower}

As you see from the above table, its very clear that 2 VDD’s “DVFS_VDD and VIRTUAL_VDD” are varied and operational VDD’s are defined as “1.08, 0.864, 0.72 0.52″

This needs careful constraining at the implementation tool level to get what you want. I will explain the commands and approach to be used at synthesis/back-end in my next posting.

Hello all,
My apologies for being inactive for last 4 weeks, I was bit busy. As per many request, here is a sample synthesis script for UPF flow……

Please note that, some of the commands used here may not be very specific to UPF, but good to have for better power optimization(for example reading vectors)

############# Script: compile.tcl ####################
############## Date : 7/08/2007 ####################
############## Author: Godwin Maben ####################

create_mw_lib -tech $mw_tech_file $dir_name
set_mw_lib_reference -mw_reference_library $mw_reference_library $dir_name
open_mw_lib $dir_name

############### Read the Verilog RTL files #######################
analyze -format verilog [ glob rtl/*.v]
set_clock_gating_style -sequential_cell latch
-minimum_bitwidth 2
-num_stage 2
-positive_edge_logic {integrated}
-neg {integrated}
-control_point before
-control_signal scan_enable

elaborate lvds_system
current_design lvds_system

link

set_tlu_plus_files -max_tluplus ./tech_file/maxtluplus.tluplus -tech2itf_map ./tech_file/tech.map

set mv_insert_level_shifter_verbose true

####### Load UPF ######################################
load_upf power_intent/lvds_system.upf

################# Source the SDC constraints #######################
source -echo ./sdc/lvds_system.sdc

##### Set the right operating conditions ###############################
set_operating_conditions -max WCCOM
set_voltage 1.08 -obj {VDD_HIGH VDD_HIGH_CRC_VIRTUAL }
set_voltage 0 -object_list {VSS}
set_voltage 0.864 -object_list {VDD_LOW VDD_LOW_RX_VIRTUAL}###########################################################
set_fix_multiple_port_nets -all -buffer_constants

extract_physical_constraints -verbose ./def/fp.def -output $NetlistDir/fp_place.tcl

create_voltage_area -coordinate {14.835 62.195 41.045 105.375 } -power_domain TX_AON
create_voltage_area -coordinate {46.425 47.875 79.385 99.97 46.425 47.84 111.41 47.875 12.53 15.115 111.41 47.84 } -power_domain CRC_GEN
create_voltage_area -coordinate {81.745 65.695 110.245 105.455 } -power_domain RECIEVER

set ptpx_map_name rtl_verilog_POWER_SYNTHESIS_map_ptpx.tcl
read_saif -input verification/dump/rtl_verilog.saif -instance tb/lvds_system
compile_ultra -timing -scan -no_autoungroup -no_seq_output_inversion -gate_clock

## Write out reports as well as Verilog/MW database for later use ###
change_names -rule verilog -hier
write -f verilog -h -out ./$NetlistDir/compile.v
write -f ddc -h -out ./$NetlistDir/compile.ddc
write_sdc -nosplit ./$NetlistDir/compile.sdc
write_link -nosplit -out ./$NetlistDir/compile.link
save_upf $NetlistDir/compile.upf

############# Insert DFT Logic ##############################
source -e scripts/dft.tcl

check_mv_design -verbose
change_names -rule verilog -hier
write_milkyway -out dft -over
get_always_on_logic -all
get_always_on_logic -cell

report_hier -nosplit -noleaf > $ReportDir/hier.rpt
report_timing -att -net -trans -cap -input -volt -nosplit > $ReportDir/timing.rpt
report_power -hier -hier_level 1 -verb > $ReportDir/power.rpt
write -f ddc -h -out ./$NetlistDir/dft.ddc
write -f verilog -h -out ./$NetlistDir/dft.v
save_upf $NetlistDir/dft.upf
exit

Based on earlier feedback, lets take a quick look at functional power state table and see how we can convert this into UPF state Table

Given below is a picture of sample Functional Power State Table

Now if you look at the above table it shows that there are 3 power domains and could be in 8 different states if we consider the active/switchable power.

But above table tells us that, there are only 5 legal states and rest of the them are not valid or illegal. Now to convert this into UPF PST, we need to first define 3 power rails.

Lets say that these 3 are called VDD_core, VDD_domain1 and VDD_domain2 respectively. Given this first we need to define the legal voltage values for these rails

add_port_state VDD_core -state {TOP_on 0.864} -state {TOP_off off}
add_port_state VDD_domain1 -state {DOMAIN1_on 1.08} -state {DOMAIN1_off off}
add_port_state VDD_domain2 -state {DOMAIN2_on 0.864} -state {DOMAIN2_off off}

Above UPF says that legal voltage values are either 1.08,0.864 or off

Now lets create a table and define the name and the columns

create_pst SYSTEM_PST -supplies {VDD_core VDD_domain1 VDD_domain2}

Now lets add the valid states to the table

add_pst_state AllOff -pst SYSTEM_PST -state {TOP_off DOMAIN1_off DOMAIN2_off}
add_pst_state LP0 -pst SYSTEM_PST -state {TOP_on DOMAIN1_off DOMAIN2_off}
add_pst_state LP1 -pst SYSTEM_PST -state {TOP_on DOMAIN1_off DOMAIN2_on}
add_pst_state LP2 -pst SYSTEM_PST -state {TOP_on DOMAIN1_on DOMAIN2_off}
add_pst_state AllOn -pst SYSTEM_PST -state {TOP_on DOMAIN1_on DOMAIN2_on}

Hopefully this gives a clear picture on how a power state table can be represented in UPF.

So far we have seen how UPF gets interpreted during synthesis and verification . Today lets look at how UPF gets interpreted during Floorplanning/Power Planning ? This is the most important phase in the design cycle, where power grid required for the design gets implemented physically to get the required functionality.

Main concerns here are

(a) If part of my design is going to be shut-down, how do I insert special cells in the power grid to cut-off power?

(b) How do I validate, whether my grid is beefed up enough to provide required amount of current to the circuit?

(c) How Many special cells are required to efficiently build the power grid ?

(d) How long will it take for the circuit to wake-up after recieving the wake-up signal ?

(e) Should I worry about the wake-up or shut-down sequence of switches as well as standard cells connected to the switches ?

(f) Which Part of the UPF conveys all these information?

First lets look at the UPF, which will be used by Floorplanning/Power Planning tools to implement the grid.

create_power_switch rx_sw
-domain RECIEVER
-input_supply_port {in VDD_LOW}
-output_supply_port {out VDD_LOW_RX_VIRTUAL}
-control_port {rx_sd power_controller/rx_sd}
-on_state {rx_on_state in {!rx_sd}}

The above command says, we need to insert a switch in the domain reciever, whose input supply port is VDD_LOW and output of the switch is VDD_LOW_RX_VIRTUAL. All the components inside the domain reciever are going to be powered through the supply net “VDD_LOW_RX_VIRTUAL”. Now how do we know which switch cell to use?

this is specified through the UPF command

map_power_switch -domain RECIEVER -lib_cell

Based on comments and feedback, I am posting the RTL as well as the UPF for this RTL. The Power Intent Diagram for this Designs is as shown Below

Power Intent Diagram

UPF for the above Power Intent:

######## Create Power Domains ###########

create_power_domain TOP
create_power_domain TX_AON -elements {transmitter power_controller}
create_power_domain RECIEVER -elements reciever
create_power_domain CRC_GEN -elements checker

## Toplevel Connections ######

# VDD_HIGH (1.08V)
create_supply_port VDD_HIGH
create_supply_net VDD_HIGH -domain TOP
create_supply_net VDD_HIGH -domain TX_AON -reuse
create_supply_net VDD_HIGH -domain CRC_GEN -reuse
connect_supply_net VDD_HIGH -ports VDD_HIGH

# VDD_LOW (0.864V)
create_supply_port VDD_LOW
create_supply_net VDD_LOW -domain TOP
create_supply_net VDD_LOW -domain RECIEVER -reuse
connect_supply_net VDD_LOW -ports VDD_LOW

# VSS (0.0V)
create_supply_port VSS
create_supply_net VSS -domain TOP
create_supply_net VSS -domain TX_AON -reuse
create_supply_net VSS -domain RECIEVER -reuse
create_supply_net VSS -domain CRC_GEN -reuse
connect_supply_net VSS -ports VSS

### RECIEVER/CRC DOMAIN Power Connections ##########

create_supply_net VDD_LOW_RX_VIRTUAL -domain RECIEVER
create_supply_net VDD_HIGH_CRC_VIRTUAL -domain CRC_GEN

### Establish Connections ################

set_domain_supply_net TOP -primary_power_net VDD_HIGH -primary_ground_net VSS
set_domain_supply_net TX_AON -primary_power_net VDD_HIGH -primary_ground_net VSS
set_domain_supply_net RECIEVER -primary_power_net VDD_LOW_RX_VIRTUAL -primary_ground_net VSS
set_domain_supply_net CRC_GEN -primary_power_net VDD_HIGH_CRC_VIRTUAL -primary_ground_net VSS

########## Shut-Down Logic for Reciever #######

create_power_switch rx_sw
-domain RECIEVER
-input_supply_port {in VDD_LOW}
-output_supply_port {out VDD_LOW_RX_VIRTUAL}
-control_port {rx_sd power_controller/rx_sd}
-on_state {state2008 in {!rx_sd}}

######### Isolation cell Settings for Reciever #######

set_isolation rx_iso_out
-domain RECIEVER
-isolation_power_net VDD_HIGH -isolation_ground_net VSS
-clamp_value 1
-applies_to outputs

set_isolation_control rx_iso_out
-domain RECIEVER
-isolation_signal power_controller/rx_iso
-isolation_sense low
-location parent

########## Create Shut-Down Logic for CRC #######

create_power_switch crc_sw -domain CRC_GEN -input_supply_port {in VDD_HIGH} -output_supply_port {out VDD_HIGH_CRC_VIRTUAL} -control_port {crc_sd power_controller/crc_sd} -on_state {state2009 in {!crc_sd}}

######### Isolation cell Settings for CRC #########
set_isolation crc_iso_in -domain CRC_GEN -isolation_power_net VDD_HIGH -isolation_ground_net VSS -clamp_value 1 -applies_to inputs

set_isolation_control crc_iso_in -domain CRC_GEN -isolation_signal power_controller/crc_iso -isolation_sense high -location parent

set_isolation crc_iso_out -domain CRC_GEN -isolation_power_net VDD_HIGH -isolation_ground_net VSS -applies_to outputs
set_isolation_control crc_iso_out -domain CRC_GEN -isolation_signal power_controller/crc_iso -location parent

#### Retention Logic for CRC ##############

set_retention crc_retain -domain CRC_GEN -retention_power_net VDD_HIGH -retention_ground_net VSS
set_retention_control crc_retain -domain CRC_GEN -save_signal {power_controller/crc_save high} -restore_signal {power_controller/crc_restore high}
map_retention_cell crc_retain -domain CRC_GEN -lib_cell_type LIB_CELL_NAME

#### Level Shifter for AON domain #################

set_level_shifter tx_aon_ls_out -domain TX_AON -applies_to outputs -location self -rule both

### Create Power State Table ##################

add_port_state VDD_HIGH -state {HighVoltage 1.08}
add_port_state VDD_LOW -state {LowVoltage 0.864}
add_port_state crc_sw/out -state {HighVoltage 1.08} -state {CRC_OFF off}
add_port_state rx_sw/out -state {LowVoltage 0.864} -state {RX_OFF off}

create_pst lvds_system_pst -supplies {VDD_HIGH VDD_LOW VDD_HIGH_CRC_VIRTUAL VDD_LOW_RX_VIRTUAL}
add_pst_state PRE_BOOT -pst lvds_system_pst -state { HighVoltage LowVoltage CRC_OFF RX_OFF}
add_pst_state CRC_ON -pst lvds_system_pst -state { HighVoltage LowVoltage HighVoltage RX_OFF}
add_pst_state RX_ON -pst lvds_system_pst -state { HighVoltage LowVoltage CRC_OFF LowVoltage}
add_pst_state ALL_ON -pst lvds_system_pst -state { HighVoltage LowVoltage HighVoltage LowVoltage}

RTL For the Top Level:

// This block needs to be Always on, it generates
// sd – shut_down for Switches
// save – save for RFF
// restore – restore for RFF
// iso – isolation_enable signals for Isolation cell
// reset – Reset signal to reset the block after wake-up
// Created on : 01/07/2008
// —————————————————————

module lvds_system ( clk, reset_n, frame_in, data_in, power_data, data_out, data_ok );
input [15:0] data_in;
input [3:0] power_data;
output [15:0] data_out;
input clk, reset_n, frame_in;
output data_ok;
wire serial_out, tx_frame, rx_frame;
wire rx_iso,crc_iso, crc_save,crc_restore, rx_sd,crc_sd,rx_power_ack,crc_power_ack;

piso transmitter ( .clk(clk), .reset_n(reset_n), .p_data_in(data_in), .load(
frame_in), .serial_out(serial_out), .tx_frame(tx_frame) );

sipo reciever ( .clk(clk), .reset_n(reset_n), .serial_in(serial_out),
.tx_frame(tx_frame), .parallel_out(data_out), .rx_frame(rx_frame) );

checker checker ( .clk(clk), .reset_n(reset_n), .load_tx_data(frame_in),
.load_rx_data(rx_frame), .tx_data(data_in), .rx_data(data_out),
.data_ok(data_ok) );

power_controller power_controller(.clock(clk),
.reset(reset_n),
.power_data(power_data),
.rx_iso(rx_iso),
.crc_iso(crc_iso),
.crc_save(crc_save),
.crc_restore(crc_restore),
.rx_sd(rx_sd),
.crc_sd(crc_sd),
.rx_power_ack(rx_power_ack),
.crc_power_ack(crc_power_ack));

endmodule

RTL for Power Controller:

RTL for Transmitter:

RTL for Reciever:

RTL for Checker: