Archive for December, 2007

UPF is a way to represent the Power Intent of a design. It directs all the tools in the flow to interpret the Power Intent in the same way. Before we jump into the details of UPF, let’s try to understand what we mean by Power Intent.

Typically for any design implementing any of the Advanced Low Power Techniques, we need to ask or have answer to the following questions:-

(a) What techniques are used to reduce power in the design?
Example: Multi-Voltage, Multi-Supply, Back-Bias, DVFS, AVFS etc.

(b) How is the design partitioned with respect to Voltage ?
Example: Core has 3 Voltages and IO has one Voltage

(c) Is there any block, whose power will be shut-down when block is not operational ?

(d) Does technology support these techniques?

(e) Are special cells such Level Shifter, Isolation Cell, Switches …. etc available in the library ?

(f) Is the architecture chosen for Power Gating, Coarse-Grain or Fine-Grain ?

(g) Is the power source internal to chip via on-chip variable regulator or an external regulator?

(h) What’s the expected Wake-Up time ? What’s the expected Ramp up Time ?

and so on.

Answers to these questions in a standard format such as UPF is the Power Intent of the design. Based on this information provided via UPF, various tools in the flow are going to make the appropriate implementation/verification decisions.

In my next post, let’s take a sample design and see how the verification tool will interpret this information.