Any design house implementing low-power ICs require a standard for describing low-power design requirements. To achieve the required power targets, design teams are increasingly adopting advanced power management techniques such as Multi-Voltage, Power Gating, Well biasing….etc. Such techniques if implemented quadruples design implementation effort and increase the risk equally. Given this the ideal way to reduce the risk is to introduce a standard that describes power intent of the designer, which can be used both by the implementation and verification team.

I found an interesting article, which talks about  requirements for power standardization.

 Low Power Standardization

Now since UPF 1.0 is already approved by Accelara, some questions that comes to my mind,for Power Gating Implementation, can UPF help us in verifying/implementing the following tasks

Since UPF is still an evolving standard, lets hope it answers all the questions that’s required to explain the power intent of the design