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    My goal is to discuss advances in design methodology, particularly in the areas of low power design and raising the level of abstraction in design above the RTL level.

    - Mike Keating

From Chaos to Structured RTL

Posted by mike keating on May 5th, 2009

Much of the RTL that I see – especially older legacy RTL – is completely unstructured. It appears (at least at first glance) to be randomly placed combational and sequential processes – always @(*), assign, and always @(posedge clk) statements. Whatever structure is in the code is defined by the position of the statements and surrounding comments. This is exactly what assembly language code looks like. And we have 30 year + experience that tells us that such unstructured code is a disaster. Modern software languages provide a rich set of construct to facilitate structured code – functions, classes, structs, unions, etc.

With the introduction of SystemVerilog, many of these same tools are available for writing structured RTL. Now we need to start using them, and migrating away from the chaotic assembly-level coding of the past.

Here is Chapter 2 of the Art of Good Design. This chapter starts outlining the process by which we migrate to structured RTL. As always, comments are more than welcome!

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3 Responses to “From Chaos to Structured RTL”

  1. Jan Decaluwe says:

    So it looks like there will finally be a high-profile publication that puts RTL designers on the right track of higher levels of abstraction. Good.

    However, you suggest that this is made possible by advances in synthesis. I challenge that view. When I started with RTL design in 1990, the techniques you describe (and higher-level ones) were perfectly supported by Synopsys DC. (Of course, some abstractions, such as enum types, were only available to VHDL designers).

    The problem never was with the tools. It is with the mindset. To realize the full potential of RTL synthesis, it is the mindset that has to change. Typically, designers have not been helped by most high-profile publications
    that favour a low level approach. Hopefully that is about to change.

  2. Jonathan Bromley says:

    This all looks extremely promising and I’m sure I’m not the only person looking forward to more like it. I just hope you’re not baying at the moon; my personal experience is that RTL design is a very conservative discipline and there is a lot of push-back against the kind of ideas you are starting to describe. What’s worse, Verilog doesn’t help; the key to making these ideas work in practice, surely, is some way to raise the level of abstraction of describing interfaces between blocks – something that Verilog is absurdly poor at doing, and SystemVerilog still hasn’t got right.

    Thanks for taking on this challenge!

  3. jesika says:

    This all looks extremely promising and I’m sure I’m not the only person looking forward to more like it. I just hope you’re not baying at the moon; my personal experience is that RTL design is a very conservative discipline and there is a lot of push-back against the kind of ideas you are starting to describe. What’s worse, Verilog doesn’t help; the key to making these ideas work in practice, surely, is some way to raise the level of abstraction of describing interfaces between blocks – something that Verilog is absurdly poor at doing, and SystemVerilog still hasn’t got right.

    Thanks for taking on this challenge!

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