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Future of Design
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    My goal is to discuss advances in design methodology, particularly in the areas of low power design and raising the level of abstraction in design above the RTL level.

    - Mike Keating

Welcome to the Future of Design

Posted by mike keating on March 31st, 2009

I recently gave a talk at SNUG that captures the key topics I propose to blog about: How the challenges of low power, productivity,  software, and verification are going to change every aspect of design over the next few years.

My central thesis in the talk is this: For the last 30 years, semiconductor technology has given us a (nearly) free ride. By scaling the CMOS transistor and lowering Vdd, we have been continuously reducing the cost, improving the power (per MIPS), and increasing the performance of chips. This free ride is now over; scaling no longer provides clear benefits or a clear technical direction for the future. Instead, we are entering an era of innovation – and of limits. Disruptive semiconductor technologies – like hi-k dielectric and metal gates,  XUV, and FINFET transitors – may keep reducing the size of transistors, but not necessarily the cost. Innovative power management techniques such as power gating and Dynamic Voltage and Frequency Scaling have dramatically reduced power in SoC during a period when semiconductor technology has not. But it is not clear that there are new (low level) design techniques that will continue to reduce power significantly.

Instead, the biggest opportunities over the next 3-5 years will be in how we use the technology we have available – how we innovate at the RTL, architectural and system level. Over the next few weeks I will be expanding on some of the ideas introduced in the SNUG talk about how we can innovate in these areas. I welcome your comments, objections, and arguments on all these topics!

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3 Responses to “Welcome to the Future of Design”

  1. Jacob Mathai says:

    Looking forward to reading your posts.

  2. Allen Mayar says:


    Regarding system level simulation, at KEMET we offer Spice models of our capacitor and also the ability to import Netlist or S-Parameters of our capacitor models to major EDA tools. I am wondering if this is something we should look into for your SW, making capacitor models exportable to the Hspice tool?
    The new low ESL and low ESR capacitors are getting more and more exposure, especially thei bavior change with Freq., temp., voltage bias and so on….

    We can make KEMET capacitor models exportable to your Hspice.

  3. Is this video available somewhere without having to register first?

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