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  • About

    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Solomon

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

Summer Blockbusters Featuring Gen4, Gen3 and M-PCIe

Posted by Scott Knowlton on August 5th, 2014

For those of you that didn’t get to see our demos at PCI-SIG DevCon, you can view these new summer blockbusters featuring the latest videos with your favorite Synopsys PCI Express Controller and PHY IP. These videos are rated two thumbs up by Scott and Richard!

If interested in the May 22nd launch of the Synopsys PCI Express solution for PCIe 4.0 before the PCI-SIG DevCon in June you can review the press release here.

On to our featured PCIe Gen4 videos, our first summer blockbuster “Industry First: PCI Express 4.0 Controller IP” features one of our PCIe Controller developers, Paul Cassidy, demoing the Synopsys PCIe 4.0 controllers. He is using coreConsultant, our GUI interface, to configure our PCIe 4.0 core to support Gen4 with 16 lanes, showing other configuration options and showing simulation results in conjunction with our PCIe 4.0 VIP. The PCIe 4.0 controllers are Rated G for Generally available!

Next in our summer blockbuster series on PCIe Gen4 is “DesignWare PHY IP for PCI Express at 16Gb/s” featuring Synopsys’ very own Rita Horner, the TMM for PCIe PHYs, showcasing our latest PHYs running at 16Gb/s in preparation for Gen4. Using a Teledyne LeCroy scope, she shows the eye diagram and other PHY related information.

If you looking for something more nostalgic like PCIe Gen3, the star of our next summer blockbuster is Synopsys’ Gen3 28nm PHY and market leading PCI Express controller in the action movie: “PCI PHY and Controller IP for PCI Express 3.0”. Our PCIe 3.0 controllers are used in over a 150 designs and presented by Torrey Lewis, R&D for PCIe Controllers and Rita Horner, the TMM for PHYs. This demo runs a lot of traffic between a PC’s system memory and our PCIe Endpoint to show the throughput of the PCIe interface. We are also using a Teledyne LeCroy logic analyzer to display the different packets going through the system. The movie went for a G rating for Generally available, but the performance of the IP pushed the rating to an R as the IP Raced through all the performance tests!

If you’re looking for power savings while maintaining the PCIe protocol, M-PCIe is showcased in “Synopsys M-PCIe Protocol Analysis with Teledyne LeCroy”. John Wiedemeier, from Teledyne LeCroy, is using their new M-PCIe Protocol Analyzer attached to the Synopsys M-PCIe Controller and Gear3 M-PHY demo. It is important as new technologies are launched to work within the ecosystem to make sure that you can talk to other products using the protocol. The Synopsys M-PCIe controllers and M-PHY IP are Rated G for Generally available!

Just in case you needed something else to go with your movies, how about some good ol’ FPGA prototyping? Mick’s Posner’s Blog “Breaking the Three Laws” had a recent posting showcasing my PCIe market data and showcasing the Synopsys PCIe 3.0 Controllers running in the Synopsys HAPS DX prototyping systems available with the new IP Prototyping Kits. If you’ve ever tried to prototype high speed device in and FPGA, then you know this can be challenging. Using the IP Prototyping Kits, this is made easy for you. If interested, you can read Mick’s Blog here.

I hope you enjoy our videos. I understand that red wine is a great accompaniment while watching :-)

For more information on the Synopsys PCIe solutions, please visit our web site.

Feel free to comment or provide suggestions on any topic that you’d like Richard or myself to discuss.

Richard and I always appreciate your support and it would be great to have you join our blog, which you can do by clicking here to subscribe.

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