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    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Solomon

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

PCI Express… in Your Disks???

Posted by Richard Solomon on August 9th, 2013

We talk here a lot about “PCI Express Everywhere” and yesterday’s release of SATA Express by the SATA-IO group formalizes PCI Express as the successor to SATA, so now PCI Express really is in your disks.  Okay, Okay, mostly in your square (solid state) disks – though I’ve heard talk from a few rotating media people that they might build some PCIe-based magnetic disk drives too.  This news won’t be a surprise to many folks however, especially those who’ve heard me talk at PCI-SIG Devcons over the last year or so. 

Keeping down the costs of cables for interfaces like SATA Express was one of the prime motivators behind the SRIS (Separate Refclk Independent SSC) ECN released by PCI-SIG back in January.  SRIS extends PCIe to support Spread Spectrum Clocking even when the two link partners do NOT share a common reference clock - which they do in typical PC add-in cards.  This allows cables like PCI-SIG’s own OcuLink or the SATA Express cable to avoid carrying and shielding a jitter-critical clock signal across them.

Aside from being a triumph of nested acronyms, that ECN set the stage for SATA-IO to specify a clever scheme by which an end user can plug either a “classic” SATA device or a new PCIe-based SATA Express device into a new SATA Express host port.  The host is responsible for detecting the type of device (via a pin on the connector) and making either a connection to a classic SATA host controller or a PCI Express x2 port.  “What? A by two PCIe port – why that?” you ask.  Well, when SATA Express was originally conceived, it was thought that the first implementations might only be PCI Express 5GT/s (Gen2) and so a x2 port was needed to make SATA Express faster than SATA 6Gb/s.  (Two lanes of 5GT/s PCIe provide 1GB/sec vs the 600MB/s of one lane of SATA 6Gb/s.)  Naturally as PCIe runs at 8GT/s today (Gen3) and 16GT/s in a few years, the SATA Express connector provides up to 2GB/s today and 4GB/s once PCIe 4.0 is completed. 

One interesting thing to me about SATA Express is that it’s invisible to software.  If a “classic” SATA device is plugged in, the host connects the SATA serial lines to its “classic” onboard SATA Host Controller – which software accesses via the AHCI programming model.  If a SATA Express device is plugged in, the host connects the PCIe serial lines to a PCIe root port and the device gets enumerated and mapped like any other PCIe endpoint would.  The magic comes about because SATA Express devices support an AHCI programming model internally – so to the operating system they look just like a “classic” SATA host controller.  Mr. Winnix can remain blissfully unaware that there is no actual SATA taking place.

I can hear you all shouting “Wait a minute now!  You just said there’s no SATA in SATA Express?!?!?”

Right! 

Brilliant isn’t it?  In one fell swoop SATA-IO has left all that messy analog PHY stuff to the wizards at PCI-SIG, and enabled a software-invisible transition to an interface better suited to the bandwidth needs of solid-state disks.  SATA Express can live on as long as software wants to support AHCI, and can leverage PCI Express speed increases until we run out of electrons.  Getting specifications through standards bodies is often described as being akin to herding cats (now you understand the intro picture) and SATA-IO has managed to neatly herd all theirs under another umbrella.

“So what does this mean for me?” you ask…  The answer depends a lot on whether you’re building a SATA Express host or a SATA Express device.  The bad news for host designers is that they are basically required to provide both a SATA host and a PCIe Root Port.  The good news for device designers is that THEY get to pick – either to be a “classic” SATA device or a SATA Express device.  “Classic” devices can keep on using whatever flavor of SATA interface they have in the past.  SATA Express devices need to implement a PCI Express x2 Endpoint (they could choose to be x1, but please don’t do that) and support the AHCI programming model.  

A word of caution: with SATA Express being all the buzz, some folks are out there selling “SATA Express” cores promising to hide all the messy bits of PCIe and AHCI (and/or NVMe even) in one big blob-o-logic.  Getting the most performance out of a PCI Express storage device generally calls for pretty tight integration between your actual non-volatile memory controller (flash, memrister, quantum nodality*, whatever) and the PCI Express interface.  Trying to use a one-size-fits-all approach here is not likely to win your product any performance accolades – ’nuff said.

 If you haven’t already clicked through the links above, please head on over to SATA-IO to see the new specification, and of course check out Synopsys’ DesignWare offerings in SATA and PCIe to see how we can enable your next SATA Express design.  If you need help, please contact us, and as always feel free to leave comments below (unless you’re a scammer peddling a weight-loss program, body-part-enhancing supplement, or other similar junk filling my comment-approval queue, in which case please send those directly to /dev/null).

Thanks for reading,

Richard

*Yes, I made that one up.

(Note that some links above are to members-only areas of PCI-SIG or SATA-IO websites, if they don’t work for you, check to see if your company is a member of those organizations.)

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