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    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Solomon

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

PCI-SIG DevCon 2013: M-PCIe with M-PHY Shifts into GEAR 3

Posted by Scott Knowlton on July 9th, 2013

In my last post, I discussed highlights from the recent 2013 PCI-SIG Developer’s Conference including PCIe 4.0, OCuLink and M-PCIe. I also provided information on the world’s first M-PCIe interoperability demo, which showcased M-PCIe solutions from Intel and Synopsys working together. I concluded with the promise of information on the second M-PCIe demo from Synopsys and more information on M-PCIe.

 If you’re new to M-PCIe, let’s start with some highlights:

 - What is M-PCIe (sometimes aka Mobile Express)?

  • M-PCIe takes the well-understood PCI Technology, used in the industry for 3 decades, and marries it with a proven mobile technology to reduce power
  • M-PCIe is an ECN to the PCI Express specification that combines the robust PCI Express protocol with the low-power MIPI M-PHY
  • M-PCIe is a PCI-SIG, not a MIPI, protocol

 - What benefits will M-PCIe give the consumer?

  • Helps usher in a new generation of high performance, lower power devices enabling mobile devices to run all day on a single battery charge without sacrificing performance or features
  • Delivers proven technology quickly to the fast-moving mobile device market. M-PCIe leverages current investments in PCI Express IP, software and know-how while reducing the time-to-market and lowering the implementation risk
  • Enables new system architectures to reduce power

 - What is Synopsys doing for M-PCIe?

  • Synopsys launched our Mobile PCI Express solution at PCI-SIG DevCon 2013, which includes M-PCIe controllers and MIPI GEAR 3 M-PHYs
  • Synopsys is committed to bringing proven technology to the market quickly and we’ve worked together with Intel to showcase the technology and do interoperability demos (see previous post)

For our second M-PCIe demo, we wanted to showcase the performance of our M-PCIe controllers and MIPI GEAR 3 M-PHYs while also showing that M-PCIe is using the standard PCI Express protocol. We decided to use our PCIe Gen3 eDMA demo and updated it to use an M-PCIe endpoint. Since there are no systems out there that have an M-PCIe Root Complex, we implemented an M-PCIe connection via a switch between the standard PC’s PCIe slot and the M-PCIe Endpoint device. The diagram below is the block diagram for the hardware in our demo overlaid onto the Synopsys HAPS FPGA prototyping system.


DesignWare M-PCIe Demo Block Diagram

Below you can see the Synopsys M-PCIe eDMA demo hardware, up and running at DevCon. The board in front is the Synopsys HAPS 62 board which has two FPGAs. The first FPGA incorporates the switch with PCIe on one side and M-PCIe on the other. The two small boards on top are the M-PHYs for the downstream port of the switch and the M-PCIe Endpoint device with the eDMA controller, with the later contained in the second FPGA on the HAPS 62. The demo is connected into a standard PC via a PCIe socket.  Note those white wires in the front of the setup are actually running true M-PCIe at its Gear3 speed!

DesignWare M-PCIe Demo

With the demo up and running, we are using the eDMA controller in the M-PCIe Endpoint to push data into the main memory of the PC over the switch. Using the eDMA controller, we can prioritize traffic and allocate bandwidth with the different read and write channels. In the screen shot below, the controls to change priority or allocation of the channels are done via the console window shown in the lower right hand corner.

DesignWare M-PCIe Screen Shot

Zooming in to the left part of the screen, we have the Windows Device Manager. Although it’s a bit difficult to see in this small picture, we have brought up the devices and our PCIe to M-PCIe switch and M-PCIe Endpoint are listed – so Windows sees them just like any other “normal” PCIe device!

DesignWare M-PCIe Demo w/Windows Device Manager

Of course, the M-PCIe devices show up in the Device Manager as a PCIe Switch and PCIe Device, which is what you expect to happen since the protocol is not changing from a system perspective.  With proven IP available now, you can quickly migrate your PCIe designs to M-PCIe and take advantage of the low power offered by using a MIPI M-PHY.

If you’re also interested our DesignWare PCIe 3.0 eDMA demo with our very own Richard Solomon presenting, you can view it on YouTube here: DesignWare PCIe 3.0 eDMA Demo

Enjoy your week and remember: Be Happy Every Day!

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