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  • About

    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Solomon

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

Do You Speak Multiprotocol?

Posted by Scott Knowlton on January 29th, 2013

For over nine years, our customers have successfully implemented Synopsys’ DesignWare® PCI Express IP into their SoCs. We just announced the new DesignWare Enterprise 10G PHY. The 28-nm PHY is multilingual, speaking PCI Express 3.0, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, CEI-6G-SR, SGMII and QSGMII and supports data rates from 1.25Gbps to 10.3Gbps per lane. With support for the IEEE Energy Efficient Ethernet (EEE) standard, the PHY’s low power consumption targets a wide range of green, high-end networking and computing applications

 You can read the DesignWare Enterprise 10G PHY press release to get more details on the new PHY.

 The PCI Express 3.0 specification completely changed the protocol definition and added multi-tap decision feedback equalization (DFE) to the continuous time linear equalization (CTLE) utilized in PCIe 1.x and PCIe 2.x. With PCI Express 3.0 using 8Gbps, the channel experiences significantly more loss over PCIe 2.0, so to compensate, enhanced equalization is necessary. DFE is complicated stuff and as people have been implementing this for PCIe 3.0, the industry has gone through some growing pains. Synopsys had a webinar on PCIe Equalization on Jan 24, 2013 if you want to learn more about this subject.

The webinar “Designing to the New PCI Express 3.0 Equalization Requirements” is designed to help you understand:

  • Why improved levels of equalization are necessary at higher data rates
  • Types of equalization enhancements required for optimal performance at 8Gbps
  • The difference between decision feedback equalization (DFE) and continuous time linear equalization (CTLE)
  • The need for equalization training and adaptability in PCIe 3.0
  • The importance of proven interoperability between the PHY and the controller

Using this new PCIe 3.0 PHY IP with the DesignWare PCI Express controller IP gives you the best PCI Express interface on the planet (no, I’m not biased). ;-) By utilizing the PCIe 3.0 controller and PHY from a single vendor you eliminate the need to navigate all of the nuances of the PIPE specification to ensure the DFE equalization works for your PCIe interface.

Click on the links below to find more information on:

DesignWare PCI Express Controller & PHY IP

DesignWare PCI Express 3.0 PHY IP

DesignWare 10G Enterprise PHY IP

Remember: Be Happy Every Day!

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