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  • About

    This blog is all about PCI Express: the wonderful ways that it enhances the products around you, the challenges designers face in implementation, and how the specification is evolving to make PCIe Express an even more useful protocol. I'll also examine how the other specifications, such as NVM Express, SATA Express and SCSI-Over-PCI Express (SOP) are leveraging PCI Express. If there is a topic that is of interest to you, feel free to "Express Yourself" by offering your insights on this blog.
  • About the Author

    Scott Knowlton

    I started out my career as a chip designer in a variety of industries and it’s likely that a few, of the more than 30 designs I’ve been responsible for, are still floating around somewhere in outer space. My IP career started at Synopsys in 1997 and over the last 15 years, I have seen tremendous changes in the semiconductor industry’s perception and adoption of IP. I started working on PCI Express in 2003 when Synopsys was getting ready to launch our first PCI Express IP solution. Since then, I have been managing the DesignWare PCI Express IP product line through all of the changes in the specification and the industry as it moves towards becoming the de-facto interconnect standard. I received a B.S.E.E from the University of Michigan (M Go Blue!), am an avid red wine drinker (love California reds) and use English as a second language when my fluency in sarcasm just doesn’t get the job done.

    Richard Soloman

    I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.

PCI Express 3.0 – Testing 1, 2, 3…

Posted by Scott Knowlton on November 29th, 2012

The PCI-SIG Compliance workshop #84 is taking place December 4-7 in Milpitas, California. At the workshop, you can test your PCIe 3.0 device as part of the “official FYI testing” to see if your product passes compliance. However, “FYI” testing is “For Your Information” and not “official testing”, so even if your product passes compliance you won’t be able to list it on the PCIe 3.0 Integrator’s list because this is only FYI testing. Based on the ramp for Gen1 and Gen2, I’d expect “official testing” for Gen 3 to begin by mid next year.

Prior to the “official FYI testing”, there was pre-FYI testing. PCI-SIG uses the pre-FYI sessions to debug the test platforms, test software, procedures, and to get some feedback on early interoperability. Synopsys and our ecosystem partners (e.g.  test equipment providers, etc.) have been working together on PCIe 3.0 testing even before PCI-SIG had pre-FYI testing.  For Synopsys, all this testing ensures that our IP is robust and interoperable with other PCIe 3.0 devices. Not only does Synopsys benefit from passing these tests, but our customers benefit as well. When our customers are spending millions to fab a chip, it’s all about reducing risks and getting their products to market fast.

Since you are all probably tired from the initial Christmas shopping on Black Friday and Cyber Monday, I thought you might want to sit back, relax and enjoy some videos. At the PCI-SIG conference in Santa Clara this year, we videotaped demos using our DesignWare PCIe 3.0 digital controllers implemented on Synopsys’ HAPS 51 FPGA-based prototyping system.

The following demo showcases the high-performance PCI Express 3.0 interface operation at 8.0 GT/s. We show the performance throughput of a PC using an endpoint application designed with DesignWare IP for PCI Express 3.0 and use a LeCroy Summit T3 Protocol Analyzer to verify compliance to the PCI Express 3.0 specification.

This second demo uses an endpoint application as the design-under-test (DUT) and we execute PCI-SIG’s gold compliance tests to demonstrate how the DesignWare IP for PCI Express 3.0 is compliant to the specification.

On a sad note, I watched “The Game” on the Saturday after Thanksgiving. “The Game” is one of the oldest rivalries in college football between The University of Michigan Wolverines and that team from down south (no, I cannot mention their name). Unfortunately, Michigan lost 26 to 21. For those who have not read my bio, I am a graduate of the University of Michigan. M Go Blue! Unfortunately, red wine didn’t help me overcome the loss!

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